ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 7

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

to occur while the DSP’s core continues to execute program
instructions. The DMA controller performs DMA transfers
between:
The DMA controller provides a number of additional features.
REV. A
Internal memory and external memory and memory-
mapped peripherals
Internal memory of other DSPs on a common bus, a host
processor, or link port I/O
External memory and external peripherals or link port I/O
External bus master and internal memory or link port I/O
REFERENCE
(OPTIONAL)
VOLTAGE
DEVICES
CLOCK
(4 MAX)
RESET
LINK
000
001
Figure 3. Shared Memory Multiprocessing System
LXDAT7–0
LXCLKIN
LXCLKOUT
LXDIR
TMR0E
BM
CONTROLIMP2–0
DS2–0
LINK
CLKS/REFS
SCLK_P
LCLK_P
S/LCLK_N
V
LCLKRAT2–0
SCLKFREQ
ID2–0
RESET
ID2–0
CLKS/REFS
IRQ3–0
FLAG3–0
RESET
REF
LINK
ADSP-TS101 #1
ADSP-TS101 #0
ADSP-TS101 #7
ADSP-TS101 #6
ADSP-TS101 #5
ADSP-TS101 #4
ADSP-TS101 #3
ADSP-TS101 #2
CONTROL
ADDR31–0
ADDR31–0
DATA63–0
CONTROL
DATA63–0
BUSLOCK
DMAR3–0
BR7–2,0
FLYBY
–7–
SDCKE
WRH/L
SDWE
BR7–1
MS1–0
MSSD
SDA10
HDQM
LDQM
BRST
BOFF
IOEN
HBG
MSH
RAS
HBR
CAS
BMS
ACK
DPA
BR1
BR0
CPA
RD
The DMA controller supports Flyby transfers. Flyby operations
only occur through the external port (DMA channel 0) and do
not involve the DSP’s core. The DMA controller acts as a conduit
to transfer data from one external device to another through
external memory. During a transaction, the DSP:
DMA chaining is also supported by the DMA controller. DMA
chaining operations enable applications to automatically link one
DMA transfer sequence to another for continuous transmission.
The sequences can occur over different DMA channels and have
different transmission attributes.
Relinquishes the external data bus
Outputs addresses, memory selects (MS1–0, MSSD,
RAS, CAS, and SDWE) and the FLYBY, IOEN, and
RD/WR strobes
Responds to ACK
ADDR
DATA
CS
RAS
CAS
WE
CKE
A10
ADDR
DATA
OE
WE
ACK
CS
CS
ADDR
DATA
ADDR
DATA
DQM
PERIPHERALS
(OPTIONAL)
PROCESSOR
(OPTIONAL)
(OPTIONAL)
INTERFACE
(OPTIONAL)
MEMORY
GLOBAL
MEMORY
EPROM
SDRAM
AND
BOOT
HOST
CLOCK
ADSP-TS101S
CLK