ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 22

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

ADSP-TS101S
Power-Up Sequencing, Power-Up Reset, and Normal
Reset (Hot) Timing Requirements
For power-up sequencing, power-up reset, and normal reset (hot
reset) timing requirements, refer respectively to
Figure
Table 19. Power-Up Sequencing Timing
Table 20. Power-Up Reset Timing
1
Parameter
Timing Requirement
t
Parameter
Timing Requirements
t
t
t
t
Applies after V
VDD
START_LO
PULSE1_HI
PULSE2_LO
TRST_PWR
6,
Table 20
1
V
V
D D ,
V
DD_IO
DD_A
V
STAT IC/STR AP
DD
V
DD
D D_ A ,
SCL K/LCLK,
, V
DD_A
V
and
RESET
V
and V
RESET Deasserted After V
SCLK/LCLK, and Static/Strap Pins are Stable
and Within Specification
RESET Deasserted for First Pulse
RESET Asserted for Second Pulse
TRST Asserted During Power-Up Reset
D D_IO ,
TRST
PINS
DD_IO
, V
Figure
DD_IO
DD_A
Stable and Within Specification After V
t
, and SCLK/LCLK and Static/Strap Pins are stable and within specification, and before RESET is deasserted.
7, and
are Stable and Within Specification
VDD
Table 21
Figure 6. Power-Up Sequencing Timing
Figure 7. Power-Up Reset Timing
and
Table 19
DD
Figure
, V
DD_A
t
S TA R T_ LO
and
8.
t
, V
T RS T _P W R
DD_IO
–22–
,
DD
t
P ULS E 1 _H I
Min
0
Min
2
50 t
100 t
2 t
SCLK
SCLK
SCLK
t
P U L S E2_ LO
Max
Max
100 t
SCLK
REV. A
Unit
ms
Unit
ms
ns
ns
ns