ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 16

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

ADSP-TS101S
Table 9. Pin Definitions—JTAG Port (continued)
1
2
3
Table 10. Pin Definitions—Flags, Interrupts, and Timer
1
2
3
Table 11. Pin Definitions—Link Ports
Signal
TDO
TMS
TRST
Type column symbols: A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 k ; pu = Internal pull-up approximately 100 k ; T = Three-state
Term (for termination) column symbols: epd = External pull-down approximately 10 k to V
nc = Not connected; au = Always used.
Signal
FLAG3–0
IRQ3–0
TMR0E
Type column symbols: A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 k ; pu = Internal pull-up approximately 100 k ; T = Three-state
Term (for termination) column symbols: epd = External pull-down approximately 10 k to V
nc = Not connected; au = Always used.
Signal
L0DAT7–0
L1DAT7–0
L2DAT7–0
L3DAT7–0
L0CLKOUT
L1CLKOUT
L2CLKOUT
L3CLKOUT
L0CLKIN
L1CLKIN
L2CLKIN
L3CLKIN
L0DIR
Type column symbols: A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 k ; pu = Internal pull-up approximately 100 k ; T = Three-state
Term (for termination) column symbols: epd = External pull-down approximately 10 k to V
nc = Not connected; au = Always used.
See the reference
The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
See
The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
See
The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
ELECTRICAL CHARACTERISTICS on Page 19
ELECTRICAL CHARACTERISTICS on Page 19
2
2
3
1
1
1
1
1
1
on Page 10
Type
O/T
I (pu
I/A (pu
Type
I/O/A
(pd
I/A (pu
O (pd
Type
I/O
I/O
I/O
I/O
O
O
O
O
I/A
I/A
I/A
I/A
O
to the JTAG emulation technical reference EE-68.
2
)
3
)
2
)
3
2
)
)
Term
nc
nc
au
Term
nc
nc
au
Term
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
1
1
Description
Test Data Output (JTAG). A serial data output of the scan path.
Test Mode Select (JTAG). Used to control the test state machine.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted or
pulsed low after power-up for proper device operation. For more information,
see
Description
FLAG pins. Bidirectional input/output pins can be used as program condi-
tions. Each pin can be configured individually for input or for output.
FLAG3–0 are inputs after power-up and reset.
Interrupt Request. When asserted, the DSP generates an interrupt. Each of
the IRQ3–0 pins can be independently set for edge triggered or level sensitive
operation. After reset, these pins are disabled unless the IRQ3–0 strap option
is initialized for booting.
Timer 0 expires. This output pulses for four SCLK cycles whenever timer 0
expires. At reset this is a strap pin. For additional information, see
on Page
Description
Link0 Data 7–0
Link1 Data 7–0
Link2 Data 7–0
Link3 Data 7–0
Link0 Clock/Acknowledge Output
Link1 Clock/Acknowledge Output
Link2 Clock/Acknowledge Output
Link3 Clock/Acknowledge Output
Link0 Clock/Acknowledge Input
Link1 Clock/Acknowledge Input
Link2 Clock/Acknowledge Input
Link3 Clock/Acknowledge Input
Link0 Direction. (0 = input, 1 = output)
for maximum and minimum current consumption for pull-up and pull-down resistances.
for maximum and minimum current consumption for pull-up and pull-down resistances.
Reset and Booting on Page
18.
–16–
SS
SS
SS
; epu = External pull-up approximately 10 k to V
; epu = External pull-up approximately 10 k to V
; epu = External pull-up approximately 10 k to V
8.
Table 16
DD-IO
DD-IO
DD-IO
REV. A