ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 32

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

ADSP-TS101S
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
–200
–220
–100
–120
–140
–160
–180
–200
–220
Figure 19. Typical Drive Currents at Strength 5
Figure 20. Typical Drive Currents at Strength 6
Figure 21. Typical Drive Currents at Strength 7
160
140
120
100
–20
–40
–60
–80
180
160
140
120
100
–20
–40
–60
–80
220
200
180
160
140
120
100
–20
–40
–60
–80
80
60
40
20
80
60
40
20
80
60
40
20
0
0
0
0
0
0
V
V
V
DD_IO
DD_IO
DD_IO
V
V
V
DD_IO
DD_IO
DD_IO
I
I
I
0.5
0.5
0.5
OL
OL
OL
= 3.15V, +85°C
= 3.15V, +85°C
= 3.15V, +85°C
= 3.15V, +85°C
= 3.15V, +85°C
= 3.15V, +85°C
1.0
1.0
1.0
OUTPUT PIN VOLTAGE – V
OUTPUT PIN VOLTAGE – V
OUTPUT PIN VOLTAGE – V
V
V
V
DD_IO
DD_IO
DD_IO
V
V
V
STRENGTH 5
STRENGTH 6
STRENGTH 7
1.5
1.5
1.5
DD_IO
DD_IO
DD_IO
= 3.3V, +25°C
= 3.3V, +25°C
= 3.3V, +25°C
= 3.3V, +25°C
= 3.3V, +25°C
= 3.3V, +25°C
2.0
2.0
2.0
V
V
V
V
V
V
DD_IO
DD_IO
DD_IO
DD_IO
DD_IO
DD_IO
2.5
2.5
2.5
= 3.45V, –40°C
= 3.45V, –40°C
= 3.45V, –40°C
= 3.45V, –40°C
= 3.45V, –40°C
= 3.45V, –40°C
I
I
I
3.0
3.0
3.0
OH
OH
OH
3.5
3.5
3.5
–32–
Test Conditions
The test conditions for timing parameters appearing in
on Page 24
output enable time, and capacitive loading. The timing specifi-
cations for the DSP apply for the voltage reference levels in
Figure
Output Disable Time
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, C
load current, I
following equation:
The output disable time t
t
t
switches to when the output voltage decays V from the
measured output high or output low voltage. The t
calculated with test loads C
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The time for the voltage on the bus to ramp by V is
dependent on the capacitive load, C
This ramp time can be approximated by the following equation:
MEASURED_DIS
MEASURED_DIS
REFERENCE
OUTPUT
Figure 22. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
22.
V
V
OL (MEASURED)
OH (MEASURED)
INPUT
SIGNAL
OR
and
and t
is the interval from when the reference signal
Figure 23. Output Enable/Disable
L
. This decay time can be approximated by the
Table 23 on Page 25
1.5V
t
DIS
DECAY
OUTPUT STOPS
t
t
MEASURED_DIS
t
DRIVING
DECAY
RAMP
as shown in
VOLTAGE TO BE APPROXIMATELY 1.5V.
DIS
L
V
V
is the difference between
and I
TEST CONDITIONS CAUSE THIS
OH (MEASURED)
OL (MEASURED)
=
t
=
DECAY
HIGH IMPEDANCE STATE.
C
---------------
C
---------------
L
L
, and with V equal to 0.5 V.
I
L
Figure
I
D
L
include output disable time,
L
, and the drive current, I
V
V
+ V
– V
t
ENA
23. The time
t
t
OUTPUT STARTS
MEASURED_ENA
RAMP
2.0V
1.0V
DRIVING
DECAY
1.5V
L
Table 22
and the
REV. A
value is
D
.