ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 12

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

ADSP-TS101S
Table 5. Pin Definitions—External Port Bus Controls
Signal
ADDR31–0
DATA63–0
RD
WRL
WRH
ACK
BMS
Type column symbols: A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 k ; pu = Internal pull-up approximately 100 k ; T = Three-state
Term (for termination) column symbols: epd = External pull-down approximately 10 k to V
nc = Not connected; au = Always used.
2
2, 4
2
2
1
1
Type
I/O/T
I/O/T
I/O/T
(pu
I/O/T
(pu
I/O/T
(pu
I/O/T
O/T
(pu/pd
3
3
3
)
)
)
3
)
Term
nc
nc
nc
nc
nc
epu
au
Description
Address Bus. The DSP issues addresses for accessing memory and peripherals
on these pins. In a multiprocessor system, the bus master drives addresses for
accessing internal memory or I/O processor registers of other ADSP-TS101S
processors. The DSP inputs addresses when a host or another DSP accesses
its internal memory or I/O processor registers.
External Data Bus. Data and instructions are received, and driven by the DSP,
on these pins.
Memory Read. RD is asserted whenever the DSP reads from any slave in the
system, excluding SDRAM. When the DSP is a slave, RD is an input and
indicates read transactions that access its internal memory or universal
registers. In a multiprocessor system, the bus master drives RD. The RD pin
changes concurrently with ADDR pins.
Write Low. WRL is asserted in two cases: When the ADSP-TS101S writes to
an even address word of external memory or to another external bus agent;
and when the ADSP-TS101S writes to a 32-bit zone (host, memory, or DSP
programmed to 32-bit bus). An external master (host or DSP) asserts WRL
for writing to a DSP’s low word of internal memory. In a multiprocessor
system, the bus master drives WRL. The WRL pin changes concurrently with
ADDR pins. When the DSP is a slave, WRL is an input and indicates write
transactions that access its internal memory or universal registers.
Write High. WRH is asserted when the ADSP-TS101S writes a long word
(64 bits) or writes to an odd address word of external memory or to another
external bus agent on a 64-bit data bus. An external master (host or another
DSP) must assert WRH for writing to a DSP’s high word of 64-bit data bus.
In a multiprocessing system, the bus master drives WRH. The WRH pin
changes concurrently with ADDR pins. When the DSP is a slave, WRH is an
input and indicates write transactions that access its internal memory or
universal registers.
Acknowledge. External slave devices can deassert ACK to add wait states to
external memory accesses. ACK is used by I/O devices, memory controllers,
and other peripherals on the data phase. The DSP can deassert ACK to add
wait states to read accesses of its internal memory. The ADSP-TS101S does
not drive ACK during slave writes. Therefore, an external (approximately
10 k ) pull-up is required.
Boot Memory Select. BMS is the chip select for boot EPROM or flash
memory. During reset, the DSP uses BMS as a strap pin (EBOOT) for
EPROM boot mode. When the DSP is configured to boot from EPROM,
BMS is active during the boot sequence. Pull-down enabled during RESET
(asserted); pull-up enabled after RESET (deasserted). In a multiprocessor
system, the DSP bus master drives BMS. For details see
on Page 8
and the EBOOT signal description in
–12–
SS
; epu = External pull-up approximately 10 k to V
Table 16 on Page
Reset and Booting
18.
DD-IO
REV. A