ADSP-2189MBSTZ-266 Analog Devices Inc, ADSP-2189MBSTZ-266 Datasheet

IC,DSP,16-BIT,CMOS,QFP,100PIN,PLASTIC

ADSP-2189MBSTZ-266

Manufacturer Part Number
ADSP-2189MBSTZ-266
Description
IC,DSP,16-BIT,CMOS,QFP,100PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet

Specifications of ADSP-2189MBSTZ-266

Interface
Host Interface, Serial Port
Clock Rate
66MHz
Non-volatile Memory
External
On-chip Ram
192kB
Voltage - I/o
3.30V
Voltage - Core
2.50V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Device Core Size
16b
Format
Fixed Point
Clock Freq (max)
66MHz
Mips
66
Device Input Clock Speed
66MHz
Ram Size
192KB
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (min)
2.25V
Operating Supply Voltage (max)
2.75/3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADSP-2189MBSTZ266

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-2189MBSTZ-266
Manufacturer:
MICROCHIP
Quantity:
16 700
Part Number:
ADSP-2189MBSTZ-266
Manufacturer:
AD
Quantity:
5 510
Part Number:
ADSP-2189MBSTZ-266
Manufacturer:
Analog Devices Inc
Quantity:
10 000
a
ICE-Port is a trademark of Analog Devices, Inc.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
REV. A
FEATURES
PERFORMANCE
13.3 ns Instruction Cycle Time @ 2.5 Volts (Internal),
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible (Easy to Use Alge-
192K Bytes of On-Chip RAM, Configured as 32K Words
Dual Purpose Program Memory for Both Instruction
Independent ALU, Multiplier/Accumulator and Barrel
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP
SYSTEM INTERFACE
Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;
16-Bit Internal DMA Port for High Speed Access to On-
4 MByte Memory Interface for Storage of Data Tables
8-Bit DMA to Byte Memory for Transparent Program
I/O Memory Interface with 2048 Locations Supports
Programmable Memory Strobe and Separate I/O
Programmable Wait-State Generation
Two Double-Buffered Serial Ports with Companding
Automatic Booting of On-Chip Program Memory from
75 MIPS Sustained Performance
Every Instruction Cycle
Power Dissipation with 200 CLKIN Cycle Recovery
from Power-Down Condition
braic Syntax), with Instruction Set Extensions
On-Chip Program Memory RAM and 48K Words On-
Chip Data Memory RAM
and Data Storage
Shifter Computational Units
Looping Conditional Instruction Execution
All Inputs Tolerate Up to 3.6 V, Regardless of Mode
Chip Memory (Mode Selectable)
and Program Overlays (Mode Selectable)
and Data Memory Transfers (Mode Selectable)
Parallel Peripherals (Mode Selectable)
Memory Space Permits “Glueless” System Design
Hardware and Automatic Data Buffering
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
GENERAL DESCRIPTION
The ADSP-2189M is a single-chip microcomputer optimized
for digital signal processing (DSP) and other high speed nu-
meric processing applications.
The ADSP-2189M combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities, and on-chip program and data
memory.
The ADSP-2189M integrates 192K bytes of on-chip memory
configured as 32K words (24-bit) of program RAM and 48K
words (16-bit) of data RAM. Power-down circuitry is also pro-
vided to meet the low power needs of battery operated portable
equipment. The ADSP-2189M is available in a 100-lead LQFP
package.
In addition, the ADSP-2189M supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking, for increased flexibility.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
DATA ADDRESS
GENERATORS
DAG 1
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
ALU
ARITHMETIC UNITS
Signaling
Final Systems
ADSP-2100 BASE
ARCHITECTURE
DAG 2
MAC
SHIFTER
SEQUENCER
FUNCTIONAL BLOCK DIAGRAM
PROGRAM
PROGRAM MEMORY DATA
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
DATA MEMORY DATA
World Wide Web Site: http://www.analog.com
DSP Microcomputer
PROGRAM
MEMORY
SPORT 0
32K
24 BIT
SERIAL PORTS
POWER-DOWN
CONTROL
MEMORY
SPORT 1
MEMORY
DATA
48K
16 BIT
ADSP-2189M
© Analog Devices, Inc., 2000
PROGRAMMABLE
TIMER
FLAGS
AND
I/O
FULL MEMORY
CONTROLLER
EXTERNAL
EXTERNAL
EXTERNAL
INTERNAL
HOST MODE
ADDRESS
BYTE DMA
DATA
PORT
DATA
DMA
BUS
BUS
BUS
MODE
OR

Related parts for ADSP-2189MBSTZ-266

ADSP-2189MBSTZ-266 Summary of contents

Page 1

... RAM and 48K words (16-bit) of data RAM. Power-down circuitry is also pro- vided to meet the low power needs of battery operated portable equipment. The ADSP-2189M is available in a 100-lead LQFP package. In addition, the ADSP-2189M supports new instructions, which include bit manipulations—bit set, bit clear, bit toggle, bit test— ...

Page 2

... ADSP-218x-based evaluation board with PC monitor software plus Assembler, Linker, Simulator and PROM Splitter software. The ADSP-218x EZ-KIT Lite is a low cost, easy to use hard- ware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features: • ...

Page 3

... The ADSP-2189M incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2189M SPORTs. For additional information on Serial Ports, refer to the ADSP-2100 Family User’s Manual, Third Edition. • SPORTs are bidirectional and have a separate, double-buff- ered transmit and receive section. • ...

Page 4

... SPORT configuration determined by the DSP System Control Register. Soft- ware configurable. Memory Interface Pins The ADSP-2189M processor can be used in one of two modes, Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities ...

Page 5

... In Idle mode IDMA, BDMA and autobuffer cycle steals still occur. Slow Idle The IDLE instruction is enhanced on the ADSP-2189M to let the processor’s internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a program- mable fraction of the normal clock rate, is specified by a select- able divisor given in the IDLE instruction ...

Page 6

... IAD15-0 Figure 2. ADSP-2189M Basic System Interface Clock Signals The ADSP-2189M can be clocked by either a crystal or a TTL- compatible clock signal. The CLKIN input cannot be halted, changed during operation, or operated below the specified frequency during normal opera- tion. The only exception is while the processor is in the power- down state. For additional information, refer to Chapter 9, ADSP-2100 Family User’ ...

Page 7

... MODES OF OPERATION Setting Memory Mode Memory Mode selection for the ADSP-2189M is made during chip reset through the use of the Mode C pin. This pin is multi- plexed with the DSP’s PF2 pin, so care must be taken in how the mode selection is made. The two methods for selecting the value of Mode C are active and passive ...

Page 8

... ADSP-2189M. Program Memory Program Memory, Full Memory Mode is a 24-bit-wide space for storing both instruction op codes and data. The ADSP-2189M has 32K words of Program Memory RAM on chip and the capability of accessing up to two 8K external memory overlay spaces using the external data bus. ...

Page 9

... Overlay 2 Memory Mapped Registers (New to the ADSP-2189M) The ADSP-2189M has three memory mapped registers that differ from other ADSP-21xx Family DSPs. The slight modifi- cations to these registers (Wait-State Control, Programmable Flag and Composite Select Control and System Control) pro- vide the ADSP-2189M’s wait-state and BMS control features. ...

Page 10

... Internal Memory DMA Port (IDMA Port; Host Memory Mode) The IDMA Port provides an efficient means of communication between a host system and the ADSP-2189M. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP’ ...

Page 11

... DMA operation. Asserting the IDMA port select (IS) and address latch enable (IAL) di- rects the ADSP-2189M to write the address onto the IAD0-14 bus into the IDMA Control Register. If Bit 15 is set to 0, IDMA latches the address. If Bit 15 is set to 1, IDMA latches into the OVLAY register ...

Page 12

... DMS, BMS, CMS, IOMS, RD, WR output drivers, • Asserting the bus grant (BG) signal, and • Halting program execution Mode is enabled, the ADSP-2189M will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-2189M is performing an external memory access ...

Page 13

... The following pins are also used by the EZ-ICE: BR, BG, RESET, and GND. The EZ-ICE uses the EE (emulator enable) signal to take con- trol of the ADSP-2189M in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The BG output is three-stated. ...

Page 14

... Three-statable pins: A0–A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7 BR Idle refers to ADSP-2189M state of operation during execution of IDLE instruction. Deasserted pins are driven to either measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 12, 13, 14), 30% are type 2 DD and type 6, and 20% are idle instructions ...

Page 15

... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2189M features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

Page 16

... V 2 CLKOUT 3.3 V Total power dissipation for this example is P Output Drive Currents Figure 14 shows typical I-V characteristics for the output drivers on the ADSP-2189M. The curves represent the current drive capability of the output drivers as a function of output voltage Symbol Value –20 θ ...

Page 17

... MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM DD INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. 4 IDLE REFERS TO ADSP-2189M STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND. Figure 15. Power vs. Frequency REV. A CAPACITIVE LOADING ...

Page 18

... ADSP-2189M TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The out- put disable time ( the difference of t DIS as shown in the Output Enable/Disable diagram. The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0 ...

Page 19

... Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). CLKIN CLKOUT * PF(3:0) RESET REV. A Min 26 0.5t – 0.5t – CKI t CKIH t CKIL t CKOH t CKH t CKL PF3 IS MODE D, PF2 IS MODE C, PF0 IS MODE A Figure 22. Clock Signals –19– ADSP-2189M Max Unit ...

Page 20

... IFS IFH the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition, for further information on interrupt servicing.) 2 Edge-sensitive interrupts require pulsewidths greater than 10 ns ...

Page 21

... asynchronous signal meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue. ...

Page 22

... ADSP-2189M Parameter Memory Read Timing Requirements: RD Low to Data Valid t RDD A0–A13, xMS to Data Valid t AA Data Hold from RD High t RDH Switching Characteristics: RD Pulsewidth t RP CLKOUT High to RD Low t CRD A0–A13, xMS Setup before RD Low t ASR A0–A13, xMS Hold after RD Deasserted t RDA ...

Page 23

... A0–A13 DMS, PMS, BMS, CMS, IOMS REV. A Min 0.5t 0.25t 0.5t 0 0.25t 0.25t 0.25t 0.75t 0.25t 0.5t t WRA WWR ASW CWR WDE Figure 26. Memory Write –23– ADSP-2189M Max Unit – – – – – – 2 0.25t + – – – DDR ...

Page 24

... ADSP-2189M Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLKIN Width SCP Switching Characteristics: t CLKOUT High to SCLKOUT CC t SCLK High to DT Enable SCDE t SCLK High to DT Valid SCDV t TFS/RFS ...

Page 25

... End of Address Latch = IS High or IAL Low Start of Write or Read = IS Low and IWR Low or IRD Low. IACK IAL IS IAD15– REV IKA t IALD t t IALP IALP t t IASU IASU t IAH Figure 28. IDMA Address Latch –25– ADSP-2189M Min Max IAH t IALS Unit ...

Page 26

... ADSP-2189M Parameter IDMA Write, Short Write Cycle Timing Requirements: IACK Low before Start of Write t IKW t Duration of Write IWP t IAD15–0 Data Setup before End of Write IDSU t IAD15–0 Data Hold after End of Write IDH Switching Characteristics: Start of Write to IACK High t IKHW ...

Page 27

... If Write Pulse ends before IACK Low, use specifications Write Pulse ends after IACK Low, use specifications This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual, Third Edition. IACK IS IWR IAD15–0 REV ...

Page 28

... ADSP-2189M Parameter IDMA Read, Long Read Cycle Timing Requirements: IACK Low before Start of Read t IKR End of Read after IACK Low t IRK Switching Characteristics: IACK High after Start of Read t IKHR IAD15–0 Data Setup before IACK Low t IKDS t IAD15–0 Data Hold after End of Read ...

Page 29

... IAD15–0 Previous Data Valid after Start of Read IRDV NOTES 1 Start of Read = IS Low and IRD Low. 2 End of Read = IS High or IRD High. REV IACK t IKR t IKHR IS t IRP IRD t IRDE PREVIOUS IAD15–0 DATA t IRDV Figure 32. IDMA Read, Short Read Cycle –29– ADSP-2189M Min Max IKDH t IKDD Unit ...

Page 30

... A11/IAD10 A12/IAD11 10 11 A13/IAD12 12 GND 13 CLKIN 14 XTAL V 15 DDEXT 16 CLKOUT GND DDINT BMS 21 DMS 22 PMS 23 IOMS 24 CMS 25 100-Lead LQFP Package Pinout ADSP-2189M TOP VIEW (Not to Scale) –30– 75 D15 74 D14 73 D13 72 D12 71 GND 70 D11 69 D10 DDEXT 66 GND D7/IWR 63 D6/IRD 62 D5/IAL 61 D4/IS 60 ...

Page 31

... The ADSP-2189M package pinout appears in the following table. Pin names in bold text replace the plain text named functions when Mode sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. ...

Page 32

... Part Number Ambient Temperature Range ADSP-2189MKST-300 0°C to +70°C ADSP-2189MBST-266 –40°C to +85°C *In 1998, JEDEC reevaluated the specifications for the TQFP package designation, assigning it to packages 1.0 mm thick. Previously labelled TQFP packages (1.6 mm thick) are now designated as LQFP. OUTLINE DIMENSIONS Dimensions shown in inches and (mm) ...

Related keywords