ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet

ADSP-TS101S

Manufacturer Part Number

ADSP-TS101S

Description

Embedded Processor

Manufacturer

Analog Devices

Datasheet

1.ADSP-TS101S.pdf (44 pages)

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REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties that

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.

COMPUTATIONAL BLOCKS

KEY FEATURES

300 MHz, 3.3 ns Instruction Cycle Rate

6M Bits of Internal—On-Chip—SRAM Memory

19 mm

Dual Computation Blocks—Each Containing an ALU, a

Dual Integer ALUs, Providing Data Addressing and

Integrated I/O Includes 14 Channel DMA Controller,

1149.1 IEEE Compliant JTAG Test Access Port for

On-Chip Arbitration for Glueless Multiprocessing with

(625-Ball) PBGA Package

Multiplier, a Shifter, and a Register File

Pointer Manipulation

External Port, Four Link Ports, SDRAM Controller,

Programmable Flag Pins, Two Timers, and Timer

Expired Pin for System Integration

On-Chip Emulation

up to Eight TigerSHARC Processors on a Bus

MULTIPLIER

DAB

SHIFTER

32x32

FILE

128

FILE

ALU

19 mm (484-Ball) or 27 mm

128

PROGRAM SEQUENCER

IAB

BTB IRQ

FETCH

ADDR

128

I/O PROCESSOR

CONTROLLER

CONTROL/

STATUS/

FUNCTIONAL BLOCK DIAGRAM

INTEGER

27 mm

TCBs

DATA ADDRESS GENERATION

DMA

32x32

J ALU

DMA ADDRESS

DMA DATA

INTEGER

32x32

K ALU

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel:781/329-4700

Fax:781/326-8703

KEY BENEFITS

Provides High Performance Static Superscalar DSP

Performs Exceptionally Well on DSP Algorithm and I/O

Supports Low Overhead DMA Transfers Between

Eases DSP Programming Through Extremely Flexible

Enables Scalable Multiprocessing Systems with Low

Operations, Optimized for Telecommunications

Infrastructure and Other Large, Demanding

Multiprocessor DSP Applications

Benchmarks (See Benchmarks in

Internal Memory, External Memory, Memory-Mapped

Peripherals, Link Ports, Host Processors, and Other

(Multiprocessor) DSPs

Instruction Set and High Level Language Friendly DSP

Architecture

Communications Overhead

MEMORY

64Kx32

256

INTERNAL MEMORY

MEMORY

64Kx32

256

Embedded Processor

I/O ADDRESS

MEMORY

LINK DATA

64Kx32

ADSP-TS101S

M0 ADDR

M0 DATA

M1 ADDR

M1 DATA

M2 ADDR

M2 DATA

CONTROLLER

LINK PORT

CONTROL/

BUFFERS

STATUS/

Table 1

SDRAM CONTROLLER

MULTIPROCESSOR

HOST INTERFACE

EXTERNAL PORT

OUTPUT BUFFER

CLUSTER BUS

OUTPUT FIFO

INTERFACE

INPUT FIFO

ARBITER

PORTS

JTAG PORT

LINK

and

www.analog.com

Table

CNTRL

ADDR

DATA

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