ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 21

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

TIMING SPECIFICATIONS
With the exception of Link Port, IRQ3–0, DMAR3–0, TMR0E,
FLAG3–0 (input), and TRST pins, all ac timing for the ADSP-
TS101S is relative to a reference clock edge. Because input
setup/hold, output valid/hold, and output enable/disable times
are relative to a clock edge, the timing data for the ADSP-TS101S
has few calculated (formula-based) values. For information on
ac timing, see
transfer timing, see
Timing on Page
General AC Timing
Timing is measured on signals when they cross the 1.5 V level as
described in
are measured between the point that the first signal reaches 1.5 V
and the point that the second signal reaches 1.5 V.
Table 17. AC Asynchronous Signal Specifications—All values in this table are in nanoseconds
1
2
Table 18. Reference Clocks
1
2
3
4
5
6
7
8
9
10
REV. A
Name
IRQ3–0
DMAR3–0
TMR0E
FLAG3–0
TRST
Signal
CCLK
CCLK
LCLK_P
LCLK_P
SCLK_P
TCK
These input pins do not need to be synchronized to a clock reference.
For output specifications, see
Actual input jitter should be combined with ac specifications for accurate timing analysis.
CCLK is the internal DSP clock or instruction cycle time. The period of this clock is equal to the Local Clock (LCLK_P) period divided by the Local
The period of CCLK is t
The Core Clock Ratio (CR) is 2, 2.5, 3, 3.5, 4, 5, or 6 as set by the LCLKRAT2–0 pins. For more information, see
See Clock Domains on Page 9.
The period of LCLK is t
LCLK_P and SCLK_P must be connected to the same source.
For more information, see
The period of SCLK is t
The period of TCK is t
Clock Ratio (LCLKRAT2–0). For information on available internal DSP clock rates, see the
10
2, 3
2, 3
1
5,7, 8, 9
4, 5, 6, 7
4, 5,6,7
1, 2
Figure 9 on Page
1
General AC
28.
Link Ports Data Transfer and Token Switch
Type
Input Local Clock
Input Local Clock
Input System Clock,
Input Test Clock (JTAG)
TCK
SCLK
LCLK
CCLK
Table 3 on Page
.
.
.
Timing. For information on link port
Table 22
.
Description
Interrupt request input
DMA request input
Timer 0 expired output
Flag pins input
JTAG test reset input
Description
Core Clock
Core Clock
SCLKFREQ = 1
27. All delays (in nanoseconds)
and
11.
Table
23.
Speed
Grade
(MHz)
250
300
250
300
All
All
Clock
Cycle
Min (ns)
4.0
3.3
or CR
or CR
Greater of 10
or CCLK
Greater of 30
or CCLK
Greater of 10
Greater of 10
–21–
Pulsewidth Low (min)
t
t
3
1 ns
The ac asynchronous timing data for the IRQ3–0, DMAR3–0,
TMR0E, FLAG3–0 (input), and TRST pins appears in
Table
The general ac timing data appears in
Table
specified in
strength set to strength 4. In order to calculate the output valid
and hold times for different load conditions and/or output drive
strengths, refer to
Page 34
Figure 33 on Page 34
Drive Strength).
CCLK
CCLK
t
4.0
(10÷3)
CCLK
+ 3 ns
+ 4 ns
17.
23. All ac specifications are measured with the load
2
4
(Rise and Fall Time vs. Load Capacitance) and
ns
Figure 24 on Page
ORDERING GUIDE on Page
Clock
Cycle
Max (ns)
12.5
12.5
CR
CR
25
Figure 25 on Page 33
12.5
12.5
(Output Valid vs. Load Capacitance and
Clock
High
Min (ns)
12.5
33, and with the output drive
Pulsewidth High (min)
t
4
3
CCLK
Table 4 on Page
{40% to 60%
{40% to 60%
{40% to 60%
Duty Cycle}
Duty Cycle}
Duty Cycle}
ADSP-TS101S
t
t
SCLK
CCLK
+ 4 ns
Table
through
Clock
Low
Min (ns)
12.5
43.
ns
ns
18,
11.
Table
Figure 32 on
Input
Jitter
Tolerance
(ps)
100
100
100
22, and
1