ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 28

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

ADSP-TS101S
Link Ports Data Transfer and Token Switch Timing
Table
Figure
cations for the link ports data transfer and token switch.
Table 24. Link Ports—Transmit
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
The formula for this parameter applies when LR is 2. At 300 MHz, the ADSP-TS101S does not run at LR =
The formula for this parameter applies when LR is 3, 4, or 8.
LxCLKIN shows the connectivity pulse with each of the three possible transitions to “Acknowledge.” After a connectivity pulse low minimum, LxCLKIN
The Link clock Ratio (LR) is 2, 3, 4, or 8 as set by the SPD bits in the LCTLx register.
This specification applies to the last data byte or the “Dummy” byte that follows the verification byte if enabled. For more information, see the ADSP-
CONNS
CONNS
CONNIW
ACKS
L
L
L
L
L
DIRS
DIRH
DOS
DOH
DOS
DOH
LDOE
LDOD
may [1] return high and remain high for “Acknowledge,” [2] return high and subsequently go low (meeting t
low for “Not Acknowledge.”
TS101 TigerSHARC Processor Hardware Reference.
X
X
X
X
X
CLK_T
CLKH_T
CLKH_T
CLKL_T
CLKL_T
1
2
1
2
5
24,
11,
1
2
3
X
4
LxCLKOUT
X
X
X
X
LxDAT7–0
Table
1
2
1
2
Figure
LxCLKIN
LxDIR
25,
12, and
Connectivity Pulse Setup
Connectivity Pulse Setup
Connectivity Pulse Input Width
Acknowledge Setup
Transmit Link Clock Period
Transmit Link Clock Width High
Transmit Link Clock Width High
Transmit Link Clock Width Low
Transmit Link Clock Width Low
LxDIR Transmit Setup
LxDIR Transmit Hold
LxDAT7–0 Output Setup
LxDAT7–0 Output Hold
LxDAT7–0 Output Setup
LxDAT7–0 Output Hold
LxDAT7–0 Output Enable
LxDAT7–0 Output Disable
Table
t
Figure 13
DIRS
26, and
t
LDOE
0
t
LxCLKH_Tx
Table 27
provide the timing specifi-
1
2
t
LxCLK_Tx
with
3
Figure 10. Link Ports—Transmit
Figure
t
4
LxCLKL_Tx
5
10,
t
6
CONNIW
t
DOS
–28–
7
t
DOH
8
t
CONNS
Min
2 t
t
0.5 t
0.9 LR 4 ns or
0.9 LR + t
whichever is larger
0.33 t
0.4 t
0.33 t
0.4 t
0.5 t
0.5 t
0.25 t
0.25 t
0.17 t
0.17 t
1
1
8
L
9
X
t
CLK_T
DOS
CCLK
10
L
L
L
L
L
X
X
X
X
X
X
L
L
L
L
L
L
t
CLK_T
CLK_T
CLK_T
CLK_T
CLK_T
ACKS
X
X
X
X
X
X
+ 1
+ 3.5
t
CLK_T
CLK_T
CLK_T
CLK_T
CLK_T
CLK_T
DOH
11
CCLK
X
X
X
X
X
X
X
X
X
X
X
12
– 1
– 1
– 1
– 1
,
13
ACKS
2; the maximum LxCLK is 125 MHz.
) for “Not Acknowledge,” or [3] remain
14
Max
1.1 LR t
0.66 t
0.6 t
0.66 t
0.6 t
2 t
2 t
15
L
L
X
X
t
CLK_T
CLK_T
LDOD
L
L
X
X
t
L
L
DIRH
CLK_T
CLK_T
X
X
CLK_T
CLK_T
X
X
CCLK
X
X
X
X
REV. A
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns