ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 25

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

Table 22. AC Signal Specifications (for SCLK <16.7 ns)—All values in this table are in nanoseconds (continued)
1
2
3
4
5
6
7
8
9
10
11
12
Table 23. AC Signal Specifications (for 16.7 ns <SCLK <25 ns)—All values in this table are in nanoseconds
REV. A
Name
CONTROLIMP2–0
DS2–0
LCLKRAT2–0
SCLKFREQ
The output valid (max) value in this column applies for the standard 30 pF capacitive load used in testing. To see how output valid varies with capacitive
The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus
CPA and DPA pins are open drains and have 0.5 k internal pull-ups.
These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference. These synchronous specifications only apply for
This pin is a strap option. During reset, an internal resistor pulls the pin low.
For input specifications, see
For additional requirement details, see
TCK_FE indicates TCK falling edge.
These pins may change only during reset; recommend connecting it to V
Name
ADDR31–0
DATA63–0
MSH
MSSD
MS1–0
RD
WRL
WRH
ACK
SDCKE
RAS
Reference clock depends on function.
System inputs are: IRQ3–0, BMS, LCLKRAT2–0, SCLKFREQ, BM, TMR0E, FLAG3–0, ID2–0, BRST, WRH, WRL, RD, MSSD, SDCKE, SDWE,
System outputs are: BMS, BM, BUSLOCK, TMR0E, FLAG3–0, FLYBY, IOEN, MSH, BRST, WRH, WRL, RD, MS1–0, HDQM, LDQM, MSSD,
loading, see
contention. The apparent driver overlap, due to output disables being larger than output enables, is not actual.
recognition in the current clock reference cycle.
CAS, RAS, ADDR31–0, DATA63–0, DPA, CPA, HBG, BOFF, HBR, ACK, BR7–0, L0CLKIN, L0DAT7–0, L1CLKIN, L1DAT7–0, L2CLKIN,
L2DAT7–0, L2DIR, L3CLKIN, L3DAT7–0, DS2–0, CONTROLIMP2–0, RESET, DMAR3–0.
SDCKE, SDWE, CAS, RAS, ADDR31–0, DATA63–0, DPA, CPA, HBG, ACK, BR7–0, L0CLKOUT, L0DAT7–0, L0DIR, L1CLKOUT, L1DAT7–0,
L1DIR, L2CLKOUT, L2DAT7–0, L2DIR, L3CLKOUT, L3DAT7–0, L3DIR, EMU.
9
Figure 33 on Page
9
9
9
Table
Description
Static pins – must be constant
Static pins – must be constant
Static pins – must be constant
Static pins – must be constant
Description
External Address Bus
External Data Bus
Memory Select HOST Line
Memory Select SDRAM Line
Memory Select for Static Blocks
Memory Read
Write Low Word
Write High Word
Acknowledge for Data
SDRAM Clock Enable
Row Address Select
34.
17.
Reset and Booting on Page
8.
DD_IO
–25–
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
/V
SS
.
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
4.2
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
ADSP-TS101S
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK