ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 34

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

ADSP-TS101S
Figure 29. Typical Output Rise and Fall Time (10%–90%,
V
Figure 30. Typical Output Rise and Fall Time (10%–90%,
V
Figure 31. Typical Output Rise and Fall Time (10%–90%,
V
DD_IO
DD_IO
DD_IO
25
20
15
10
25
20
15
10
25
20
15
10
5
0
5
0
5
0
= 3.3 V) vs. Load Capacitance at Strength 4
= 3.3 V) vs. Load Capacitance at Strength 5
= 3.3 V) vs. Load Capacitance at Strength 6
0
0
0
y = 0.1001x + 0.7763
y = 0.1071x + 0.9877
10
10
y = 0.0946x + 1.2187
10
RISE TIME
RISE TIME
RISE TIME
20
20
20
30
30
30
LOAD CAPACITANCE – pF
LOAD CAPACITANCE – pF
LOAD CAPACITANCE – pF
(V
40
(V
(V
STRENGTH 4
40
40
STRENGTH 5
STRENGTH 6
DD_IO
DD_IO
DD_IO
50
50
50
= 3.3V)
= 3.3V)
= 3.3V)
60
60
60
y = 0.0798x + 1.0743
70
70
70
FALL TIME
y = 0.0906x + 0.4597
y = 0.0793x + 0.8691
80
80
80
FALL TIME
FALL TIME
90
90
90
100
100
100
–34–
1
The line equations for the output valid versus load capacitance are:
Figure 33. Typical Output Valid (V
Capacitance at Max Case Temperature and Strength 0–7
Strength 0: y = 0.0956x + 3.5662
Strength 1: y = 0.0523x + 3.2144
Strength 2: y = 0.0433x + 3.1319
Strength 3: y = 0.0391x + 2.9675
Strength 4: y = 0.0393x + 2.7653
Strength 5: y = 0.0373x + 2.6515
Strength 6: y = 0.0379x + 2.1206
Strength 7: y = 0.0399x + 1.9080
Figure 32. Typical Output Rise and Fall Time (10%–90%,
V
DD_IO
25
20
15
10
15
10
5
0
5
0
= 3.3 V) vs. Load Capacitance at Strength 7
0
0
y = 0.0907x + 1.0071
10
10
RISE TIME
20
20
30
30
LOAD CAPACITANCE – pF
LOAD CAPACITANCE – pF
STRENGTH 0-7
(V
(V
40
40
STRENGTH 7
DD_IO
DD_IO
50
50
= 3.3V)
= 3.3V)
60
60
DD_IO
70
70
y = 0.09x + 0.3134
= 3.3 V) vs. Load
80
80
FALL TIME
90
90
100
100
REV. A
0
1
2
3
4
5
6
7
1