ADSP-TS101S Analog Devices, ADSP-TS101S Datasheet - Page 18

• Manufacturer Part Number: ADSP-TS101S
• Description: Embedded Processor
• Manufacturer: Analog Devices

ADSP-TS101S
Table 15. Pin Definitions—Power, Ground, and Reference
STRAP PIN FUNCTION DESCRIPTIONS
Some pins have alternate functions at reset. Strap options set
DSP operating modes. During reset, the DSP samples the strap
option pins. Strap pins have an approximately 100 k pull-down
for the default value. If a strap pin is not connected to an external
pull-up or logic load, the DSP samples the default value during
reset. If strap pins are connected to logic inputs, a stronger
external pull-down may be required to ensure default value
Table 16. Pin Definitions—I/O Strap Pins
Signal
V
V
V
V
V
V
NC
Type column symbols: A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 k ; pu = Internal pull-up approximately 100 k ; T = Three-state
Term (for termination) column symbols: epd = External pull-down approximately 10 k to V
nc = Not connected; au = Always used.
Signal
EBOOT
IRQEN
TM1
TM2
DD
DD_A
DD_IO
REF
SS
SS_A
Type
P
P
P
I
G
G
—
On Pin…
BMS
BM
L2DIR
TMR0E
Term
au
au
au
au
au
au
Description
EPROM boot.
Interrupt Enable.
Test Mode 1.
Test Mode 2.
0 = boot from EPROM immediately after reset (default)
1 = idle after reset and wait for an external device to boot DSP through the
0 = disable and set IRQ3–0 interrupts to level sensitive after reset (default)
1 = enable and set IRQ3–0 interrupts to edge sensitive immediately after reset
0 = required setting during reset.
1 = reserved.
0 = required setting during reset.
1 = reserved.
external port or a link port
Description
V
V
V
Reference voltage defines the trip point for all input buffers, except RESET,
IRQ3–0, DMAR3–0, ID2–0, CONTROLIMP2–0, TCK, TDI, TMS, and
TRST. The value is 1.5 V ± 100 mV (which is the TTL trip point). V
be connected to a power supply or set by a voltage divider circuit. The voltage
divider should have an HF decoupling capacitor (1 nF HF SMD) connected to
V
DSP’s pins as possible.
Ground pins.
Ground pins for analog circuits.
No connect. Do not connect these pins to anything (not to any supply, signal,
or each other), because they are reserved and must be left unconnected.
DD
DD
DD
SS
. Tie the decoupling capacitor between V
pins for internal logic.
pins for analog circuits. Pay critical attention to bypassing this supply.
pins for I/O buffers.
–18–
depending on leakage and/or low level input current of the logic
load. To set a mode other than the default mode, connect the
strap pin to a sufficiently stronger external pull-up. In a multi-
processor system, up to eight DSPs may be connected on the
cluster bus, resulting in parallel combination of strap pin pull-
down resistors.
strap pins.
See Filtering Reference Voltage and Clocks on Page 9.
SS
; epu = External pull-up approximately 10 k to V
Table 16
lists and describes each of the DSP’s
REF
input and V
SS
, as close to the
DD-IO
REF
REV. A
can