L64724 LSI Logic Corporation, L64724 Datasheet - Page 73

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.8 Viterbi Maximum Bit Error Count, Rate 2/3 (Group 4: APR 9)
Whenever the symbol error count from the internal bit error counter
exceeds the value VMBEC_1_2[7:0], the synchronization module
concludes that the Viterbi decoder module is out of synchronization and
proceeds to adjust the phase of the incoming symbol stream until
synchronization is reached. The symbol error count is given by
Equation
Equation 3.3
For example, a value of VMBEC_1_2[7:0] = 0x03 specifies 416 errors.
For more information, see
Note that a software reset (FEC_RST, APR 55, bit 0) does not affect the
contents of the register.
Read/Write: R/W
This register specifies the maximum number of Viterbi symbol errors that
are allowed to occur within the data period set by VMDC1 (Group 4,
APR 4) to achieve Viterbi module synchronization.
Whenever the symbol error count from the internal bit error counter
exceeds the value VMBEC_2_3[7:0], the synchronization module
concludes that the Viterbi decoder module is out of synchronization and
proceeds to adjust the phase of the incoming symbol stream until
synchronization is reached. The symbol error count is given by
Equation
Equation 3.4
Group 4: Configuration Registers
APR
Number of Symbol Errors
8
Number of Symbol Errors
Note:
Note:
D7
3.3.
3.4.
This register is used during Viterbi code rate acquisition for
Rate 1/2.
This register is used during Viterbi code rate acquisition for
Rate 2/3.
Viterbi Maximum Bit Error Count VMBEC_1_2[7:0], Rate 1/2
Section 7.1.3, “Viterbi BER Monitor,” page 7-7.
=
=
128 VMBEC_1_2
128 VMBEC_2_3
+
+
32
32
D0
3-43