L64724 LSI Logic Corporation, L64724 Datasheet - Page 245

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Group 4, APR 3 – Set to 0x09.
Clear the VCR[2:0] bits (D7 to D5) to 0x00 for rate 1/2, the TEI bit (D4)
to 0 or 1, set the SYNC2_MOD bit (D3) to 1, clear bit D2 to 0, and based
on Section 4.2, set the PLL_M[1:0] bits to 0x01.
Group 4, APR 4 – Set to 0x40.
Since the Viterbi code rate is 1/2, based on the graph shown in
Figure 6.4
VMBEC/VMDC1 establishes a valid decision threshold over the entire
SNR range.
VMDC1.
Equation B.37
Choosing VMDC1[7:0] = 64 (0x40) yields a value of 30 (0x1E) for
VMBEC[7:0].
Group 4, APR 5–7 – Set to 0x0F0000.
The VMDC2[23:0] bits select a second window. The VMDC2[23:0] bits
control the window size over which Viterbi errors are counted and are
used for calculating the BER, not for the auto-synchronization that is
controlled by VMDC1. In this example, choose a window size of
3.932 x 10
Set Group 4, APR 7 to 0x0F, APR 6 to 0x00, and APR 5 to 0x00.
QPSK Demodulator and FEC Configuration Example: Low Data Rates
0.24
=
128 VMBEC
--------------------------------------------- -
6
for an E
Equation B.37
256 VMDC 1
bits = VMDC2[23:0] x 4. Other values may work as well.
b
/N
+
o
32
= 4.0 (E
shows the relationship between VMBEC and
s
/sigma^2 = 7.0,) a choice of 0.24 for
B-31