L64724 LSI Logic Corporation, L64724 Datasheet - Page 70

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.4 PLL Parameter M, Transport and Viterbi Code Rate Select
3-40
(Group 4: APR 3)
The PLL Configuration Parameter M (PLL_M[1:0]) configures the PLL
module for clock synthesis. This register also contains bits to set the
Viterbi Decoder module code rate and configure the Transport Error
Indicator.
Read/Write: R/W
VCR
TEI
L64724 Registers
APR
3
Viterbi Code Rate, VCR[2:0]
D7
Viterbi Code Rate
Set these VCR bits to select the code rate for the L64724
Viterbi decoder module. The three bits are assigned as
follows:
The VCR bits are disregarded when automatic Viterbi
rate acquisition is selected (Auto Rate bit: Group 4,
APR 15, D6 = 1.)
Transport Error Indicator Select
When the Transport Error Indicator Select bit is set to 1,
it activates the transport error indicator mechanism. In
this mode, the first bit following the synchronization byte
in a Transport Packet is forced HIGH whenever the Reed-
Solomon decoder finds the data block to be
uncorrectable. Otherwise, it remains unchanged. When
the TEI bit is cleared to 0, the transport error indicator will
not be set at any time (see the MPEG-2 System
0
0
0
0
1
1
1
1
VCR[2:0]
D5
0
0
1
1
0
0
1
1
TEI
D4
0
1
0
1
0
1
0
1
SYNC2_
MOD
D3
Definition
Rate 1/2
Rate 2/3
Rate 3/4
Rate 5/6
Rate 6/7
Rate 7/8
Unused
Unused
Reserved
D2
D1
PLL_M[1:0]
D0
[7:5]
4