L64724 LSI Logic Corporation, L64724 Datasheet - Page 268

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

C.4 Programming for 3-Wire Mode
C.4.1 Single Data Write
C.4.2 Two Data Writes
C.4.3 Multiple-Data Writes
C-6
To set the Serializer in a mode to produce 3-wire interface compliant
signals on the SDATA (XCTR_OUT[1]), SCLK (XCTR_OUT[0]), and the
ENABLE (XCTR_OUT[2]) signals, the Serial_C register (Group 4,
APR 62[6:5]) must be programmed as shown in the table below:
Follow the steps outlined below, written as pseudo-code, to address the
slave and perform subsequent write cycles to it.
1. Write TXED (8-bit data)
1. Write STXD (8-bit slave-address)
2. Wait (11 SCLK cycles)
3. Write TXED (8-bit data)
1. Write STXD (8-bit data)
2. Wait (11 SCLK cycles){
3. for (i =1; i < #data_bytes; i++)
Figure C.2
Programming the Serializer
Serial_C[1:0]
0
1
1
}
Write TXED(8-bit data)
Note:
1
0
1
shows the 3-wire Serializer operation.
Write STXD(8-bit data)
Wait (11 SCLK cycles)
Only writes to a 3-wire compliant slave can be
accomplished using the Serializer—it does not perform
read operations.
Selected Function
3-wire interface, ENABLE HIGH for all valid data
3-wire interface, ENABLE HIGH for 1 clock cycle at the start
of data transfer
3-wire interface, ENABLE HIGH for 1 clock cycle at the end
of data transfer