L64724 LSI Logic Corporation, L64724 Datasheet - Page 160

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

6-4
Figure 6.3
Q Input
This first synchronization stage does not inspect the data stream for
specific synchronization patterns, nor does it remove any portions of the
data stream. Once the Viterbi Decoder module has reached
synchronization, the Deinterleaver and Reed-Solomon blocks in the data
pipeline each require their own synchronization procedures.
The data bit count and bit error count threshold values are VMDC1
(Group 4, APR 4) and VMBEC (Group 4, APR 8–13.) To assist you in the
proper selection of the ratio (VMBEC/VMDC1) of the threshold values,
Figure 6.4
Rate vs. SNR for all the code rates that the L64724 supports. The upper
curve in each graph represents the out-of-synchronization condition, and
the lower curve represents the in-synchronization condition.
Decoding Pipeline Synchronization
Q Input
I Input
I Input
through
Phase Rotation for Synchronization
Phase Rotation
Figure 6.9
show the plots of the Channel Symbol Error
Q Output = I Input
I Output = Q Input
Q Output = Q Input
I Output = I Input