L64724 LSI Logic Corporation, L64724 Datasheet - Page 216

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

B.1.1 Automatic Gain Control (AGC) Loop
B.1.1.1 Group 4, APR 21—Set to 0x00
B.1.1.2 Group 4, APR 21–23—Set to 0x00
B.1.1.3 Group 4, APR 24
B.1.1.4 Group 3, APR 10
B-2
The AGC loop must lock first. When the AGC loop is closed, the signal
level at the analog-to-digital converter (ADC) input is 0.588 (1/1.7) times
the ADC range, assuming the PWR_REF register (Group 4, APR 24) is
set to its correct value and DF_GAIN = 1.
A simple test that you can perform is to change the power of the
transmitted signal and observe the I or Q channels with an oscilloscope
just before the ADC input. Make sure that the peak-to-peak signal range
is about 1/1.7 of the peak-to-peak ADC range. Also check that the AGC
can keep the signal level fixed, even when the transmitted power is
changed. Observe that the AGC voltage at the loop output is changing
with the changes in the transmitted power. You may need to toggle the
PWRP bit (Group 4, APR 54) to switch the polarity of the PWRP output.
The parameters in the following subsections are related to the AGC loop.
Clear the PLL_BP bit to 0 to enable the internal PLL to generate the A/D
clock. Clear the CLK_DIV1[4:0] bits to 0 because the internal PLL is
used. Set Group 4, APR 21 to 0x00.
Set Group 4 APR 21 and 23 to 0x00, because the CLK_DIV bits are
unused when the internal PLL has been selected.
The PWR_REF[7:0] parameter controls the signal level at the input of the
ADC. It should be set to the value given in
The PWR_LVL[7:0] field is proportional to the mean value of the AGC
level. With an AGC amplification range of 0 dB to
shows the corresponding PWR_LVL settings and amplification levels.
L64724 Application Notes
Equation 5.26,
40 dB,
on
Table B.1
page
5-21.