L64724 LSI Logic Corporation, L64724 Datasheet - Page 246

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Group 4, APR 8 – Set to 0x1E.
Equation B.37
yields a value for VMBEC[7:0] of 30 or 0x1E.
Group 4, APR 9–13 – Set all these registers to 0x00.
Group 4, APR 14 – Set to 0x47.
The DVB Synchronization Word[7:0] value is 0x47.
Group 4, APR 15 – Set to 0x10.
Clear D7 to 0, clear the Auto Rate bit (D6) to 0 to obtain the code rate
from the VCR, clear the D5 and D4 bits to 0, clear the IMQ_EN bit (D3)
to 0 for IMQ to be determined by APR 2 bit 7, clear the Di_Bypass bit
(D2) to 0 to enable the deinterleaver, and clear the L[1:0] bits (D1, D0)
to 0x00 to select zero mismatching bits.
Group 4, APR 16 – Set to 0x00.
Clear D7 and D6 to 0, clear the SSS[1:0] bits (D5 and D4) to 0 to select
Viterbi decoder sync, clear the SSA[1:0] bits D3 and D2 to 0x00 to set
the number of sync words to acquire to three, and clear the SST[1:0] bits
(D1 and D0) to 0 to set the number of missed sync words to loss of lock
at two.
Group 4, APR 17 – Set to 0x00.
Clear the D7 and D6 bits to 0, clear the OF bit (D5) to 0 for serial channel
output mode, and clear the OS[4:0] bits (D4 to D0) to 0 to observe the
descrambler output.
Group 4, APR 18 – Set to 0x00.
Write any value to this register to reset the PLL module.
Group 4, APR 19 – Set to 0x7A.
Select the register bits according to the following table.
B-32
L64724 Application Notes