L64724 LSI Logic Corporation, L64724 Datasheet - Page 26

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

2.5 AGC/Clock Control Interface
2.6 Channel Data Output Interface
2-6
XCTR_OUT[2:0]
PWRP
The Channel Data Output Interface is the output path from the L64724.
It is typically connected to the input of the transport demultiplexer in a
set-top decoder application.
BCLKOUT
CO[7:0]
L64724 Signal Definitions
Control Output
The XCTR_OUT[2:0] pins are external output control
pins. They are set by programming the corresponding bits
in the Group 4, APR 55 register. XCTR_OUT[1] can
function as the Serial Clock (SCLK) signal, and
XCTR_OUT[0] can function as the Serial Data (SDATA)
signal.
Power Control
The PWRP signal is the positive modulated output used
for power control and can drive an external passive RC
filter that feeds the tuner gain control stage.
Byte Clock Out
The BCLKOUT output signal is a strobe that indicates
valid data bytes on the CO[7:0] bus when the L64724 is
in Parallel Channel Output mode. The BCLKOUT signal
cycles once every valid output data byte and is used by
the transport demultiplexer to latch output data from the
L64724 at the BCLKOUT rate. The BCLKOUT signal
must be disregarded in Serial Channel Output mode.
Channel Data Out
The CO[7:0] signals form the decoded output data port.
When the OF bit is 1 (Group 4, APR17), the L64724
operates in the Parallel Channel Output mode. In this
mode, the L64724 outputs the channel data as 8-bit wide
parallel data on the CO[7:0] signals. In Serial Channel
Output mode (OF = 0) the L64724 outputs the channel
data as serial data on CO[0]. The data is latched on
every bit clock cycle. The chronological ordering in Serial
Channel output mode is MSB oldest, LSB newest.
Output
Output
Output
Output