L64724 LSI Logic Corporation, L64724 Datasheet - Page 66

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Table 3.5
3-36
(Sheet 3 of 4)
APR
[5:0]
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
CLK_SWP
Clock Loop Lambda, CLK_LAMBDA_SEL[3:0]
SNR_EST
Reserved
ADC_BP
_SWAP
SWAP
SWP_
CAR_
D7
Group 4 Register Map (Cont.)
L64724 Registers
ERROR_
ERROR_
PWRP_
OB_2C
SWAP
SWAP
CAR_
CLK_
TRI
D6
Clock Synchronizer Upper Sweep Limit, CLK_USWL[15:8]
Clock Synchronizer Lower Sweep Limit, CLK_LSWL[15:8]
Clock Synchronizer Upper Sweep Limit, CLK_USWL[7:0]
Clock Synchronizer Lower Sweep Limit, CLK_LSWL[7:0]
Carrier Loop Filter Initialization, CAR_LF_INIT[23:16]
Carrier Loop Filter Initialization, CAR_LF_INIT[15:8]
Carrier Loop Filter Initialization, CAR_LF_INIT[7:0]
Clock Synchronizer Sweep Rate, CLK_SWR[15:8]
Clock Synchronizer Sweep Rate, CLK_SWR[7:0]
ADC_PD
AUTO_
AUTO_
CAR_
CLK_
External Control Output Bits, XCTR[3:0]
SWP
SWP
Clock Loop Bias, CLK_BIAS[23:16]
D5
Clock Loop Bias, CLK_BIAS[15:8]
Clock Loop Bias, CLK_BIAS[7:0]
Clock Loop Bias, CLK_BIAS[30:24]
Set to 1
LOCK_
LEN
FP_
D4
Reserved
Reserved
Reserved
CLK_SEL
PWRP
AGC_
D3
Clock Loop Mu, CLK_MU_SEL[3:0]
PED_SEL
Reserved
CAR_
D2
Reserved
DEMOD
OPEN
OPEN
CAR_
_RST
CLK_
D1
CAR_SW
CLK_SW
ALPHA_
CLK_
FEC_
RST
SEL
DO