L64724 LSI Logic Corporation, L64724 Datasheet - Page 283

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Table E.2
Group 4
(Sheet 3 of 5)
(Cont.)
C_ADD
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
Microcontroller Address Map (Cont.)
Microcontroller Address Map
P_APR
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
4
5
6
7
8
9
PCLK_
Sync_
Dem_
BER
Step
Carrier Phase Lock Detector Threshold, CAR_LC_THSL[7:0]
INV
BP
D7
BF
Viterbi Max Data Bit Count 2, VMDC2[15:8], middle byte
CAR_LAMBDA_SEL[3:0]
Viterbi Max Data Bit Count 2, VMDC2[23:16], high byte
DF_Select[2:0]
Carrier Loop Lambda,
Viterbi Max Data Bit Count 2, VMDC2[7:0], low byte
Reserved]
Viterbi Maximum Bit Error Count[7:0], Rate 1/2
Viterbi Maximum Bit Error Count[7:0], Rate 2/3
Viterbi Maximum Bit Error Count[7:0], Rate 3/4
Viterbi Maximum Bit Error Count[7:0], Rate 5/6
Viterbi Maximum Bit Error Count[7:0], Rate 6/7
Viterbi Maximum Bit Error Count[7:0], Rate 7/8
Freeze
Enable
Sync2
Sync2
ST1_
PLL_
Rate
Auto
RST
Scale factor for DEMI, DEMQ, SCALE[7:0]
SNR Estimator Threshold, SNR_THS[7:0]
D6
BP
BP
Viterbi Max Data Bit Count, VMDC1[7:0]
Reserved
RAM
Synchronization Word[7:0]
Ber_
Sync Status
Res.
Test
Nor
OF
D5
SSS[1:0]
Select,
PWR_REF[7:0]
CLK_DIV2[7:0]
PLL_RESET
New_
DF_Gain[1:0]
Ber
PD
D4
Output Selector, OS[4:0]
Acq, SSA [1:0]
IMQ_
Sync States
EN
D3
CLK_DIV2[12:8]
CLK_DIV1[4:0]
CAR_MU_SEL[3:0]
Carrier Loop Mu,
DI_By
pass
INT_
DC
D2
DF_Ratio[2:0]
Sync States
D1
PWR_BW
SST[1:0]
Track,
L[1:0]
[1:0]
20_35
MF_
DO
R/W
R/W
by
E-7
C