L64724 LSI Logic Corporation, L64724 Datasheet - Page 6

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

Figures
vi
1.1
1.2
2.1
3.1
3.2
3.3
3.4
3.5
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
Contents
L64724 Block Diagram
Set-Top Decoder Box Block Diagram
L64724 Logic Symbol
Register File Structure
Issue a Hard Reset
Initialize APR0 and APR1 to Zero
Write Locations 0 and 1 in Group 4
Read Back Group 4
L64724 Clocking: Internal PLL
PLL Clock Synthesis
L64724 Functional Blocks in the Decoding Pipeline
CLK and Analog Inputs for Channel Data Input
CLK and Digital Inputs for ADC Bypass Mode
Parallel Output Interface Waveforms
Descrambler Parallel Output Waveforms
Descrambler Serial Output Waveforms
Demodulator Module and Associated Circuitry
Input Quantization
Clock Recovery Loop
Timing Loop Sweep Operation
Carrier Recovery Loop
Frequency Sweeping
SNR Threshold vs. E
Carrier Loop Filter Parameters
Eye Pattern and ADC Range
AGC Loop Control
Synchronization Module
Viterbi Decoder Synchronization
Phase Rotation for Synchronization
Channel Symbol Error Rate vs. SNR for Rate = 1/2 Code
Channel Symbol Error Rate vs. SNR for Rate = 2/3 Code
Channel Symbol Error Rate vs. SNR for Rate = 3/4 Code
Channel Symbol Error Rate vs. SNR for Rate = 5/6 Code
Channel Symbol Error Rate vs. SNR for Rate = 6/7 Code
Channel Symbol Error Rate vs. SNR for Rate = 7/8 Code
Reed-Solomon, Deinterleaver Synchronization
s
/N
o
4-12
4-13
4-13
4-15
4-16
4-17
5-11
5-12
5-13
5-17
5-17
5-20
5-22
1-2
1-4
2-2
3-3
3-5
3-5
3-6
3-6
4-2
4-4
5-2
5-3
5-8
6-2
6-3
6-4
6-5
6-5
6-6
6-6
6-7
6-7
6-8