L64724 LSI Logic Corporation, L64724 Datasheet - Page 107

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.48 Timing Lock Detector Threshold (Group 4: APR 69)
3.7 Group 5: Self-Tuning Microcontroller Registers
Table 3.6
(Sheet 1 of 2)
APR
0
1
1. Serial Mode is the recommended interface mode. LSI Logic does not recommend parallel
mode for new designs.
D7
Group 5 Register Map
F
F
This register contains the control bits for the Timing Lock Detector
Threshold.
Read/Write: R/W
CLK_LC_THSL[7:0]
Group 5 contains the memory space for instructions and configuration for
the microprogrammed controller (uC). The registers can be accessed
through the chip-level serial or parallel interface
Table 3.6
Group 5: Self-Tuning Microcontroller Registers
APR
symbol
sample
D6
69
Note:
Unused
= Symbol Clock Frequency
= Sampling Clock Frequency
D7
shows the addresses and fields of the Group 5 registers.
D5
These registers are write-only and the internal scratch pad
registers are not visible to the host microprocessor.
Timing Lock Detector Threshold Select
Program these bits to select the threshold values for the
timing lock detector mechanism.
Timing Lock Detector Threshold, CLK_LC_THSL[7:0]
uC-Instruction 0 [7:0]
D4
D3
uC Instruction 0 [11:8]
D2
1
.
D1
D0
D0
[7:0]
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