L64724 LSI Logic Corporation, L64724 Datasheet - Page 71

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.6.5 Viterbi Maximum Data Bit Count 1 (Group 4: APR 4)
SYNC2_MOD Sync2 Modified
Reserved
PLL_M
This register specifies the number of valid symbols, divided by 256, over
which the number of Viterbi decoded symbol errors are counted for
synchronization. For example, a value of VMDC1[7:0] = 0x02 specifies
512 data bits.
Equation 3.1
Group 4: Configuration Registers
VMDC1
=
Symbols
------------------------ -
Specification H.222 Transport Stream Packet Layer, para-
graph 2.4.3.2). Using the TEI feature allows a simpler
interface to the LSI Logic L64007 Transport
Demultiplexer. For more information, see the LSI Logic
L64007 MPEG-2, DVB, and TSAT Transport
Demultiplexer Technical Manual .
The SYNC2_MOD bit selects an alternate method of
acquiring Sync 2. It should be set to 1 for normal
operation.
Reserved
This bit must be cleared to 0 for proper operation.
VCO Frequency Range for PLL Module
PLL_M is one of four parameters (PLL_S, PLL_N, PLL_T,
and PLL_M) that you must set to configure the PLL
module for clock synthesis. For more information see
Section 4.2, “PLL Clock Generation,” page 4-3.
the PLL_M[1:0] bits to tell the L64724 the frequency
range of the PLL.
256
PLL_M[1:0]
0
0
1
1
0
1
0
1
PLL Range
40–50 MHz
50–60 MHz
60–70 MHz
70–90 MHz
Configure
[1:0]
3-41
3
2