L64724 LSI Logic Corporation, L64724 Datasheet - Page 154

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L64724

Manufacturer Part Number
L64724
Description
Satellite Receiver
Manufacturer
LSI Logic Corporation
Datasheet

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5.8.3 Power Level
5.9 Output Control
5-22
Figure 5.10 AGC Loop Control
PWR
The R and C values for the passive low-pass filter should meet the
requirements of
Equation 5.27
The L64724 stores the AGC loop control voltage in the PWR_LVL[7:0]
register (Group 3, APR 10), where the microcontroller can monitor it. The
relationship between the loop voltage V
is shown in
Equation 5.28
The PWRP pin uses an open drain buffer that allows you to apply an
external V
Because the output of the matched filter is quantized to four bits for the
subsequent Viterbi decoder, the L64724 Output Control properly adjusts
the level of the output signals.
The microcontroller can adjust the level of the demodulated DEMI and
DEMQ output signals using the SCALE register (Group 4, APR 26). The
SCALE register multiplies the results of the matched filter before it is
truncated to the 4-bit outputs.
Demodulator Module Functional Description
R
V
AGC
AGC
C
=
AGC
REF
PWR_LVL
--------------------------- -
Equation
256
voltage of 5 V even if the L64724 is powered at 3.3 V.
N
P
64 s
Equation
5 V
R ~ 470
5.28.
V
REF
5.27.
R
AGC
~ 2.7 K
AGC
and the PWR_LVL register
C
AGC
~ 22 nF
V
AGC

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