L64724 LSI Logic Corporation, L64724 Datasheet - Page 136

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

5.4 Decimation Filters
Table 5.1
1. Megasymbols per second (MS/s)
2. For Rs <= 44.5 MS/s, calculate the sampling rate as follows: from the set of valid sampling frequency
5-4
7.5 to 3.75
Threshold
45 to 44.5
44.5 to 30
15 to 7.5
3.75 to 1
30 to 15
(MS/s
values, (30, 35, 40 ..., 85, 90), select the lower, closest value to 4 * DF_RATIO * Rs/(1 + alpha),
where alpha is the “corner” margin (1%).
Rs
1
)
DF_RATIO DF_SELECT DF_GAIN
Decimation Procedure
1
1
1
2
4
8
The L64724 implements decimation filters on each I and Q branch. The
following decimation ratios can be selected through the DF_RATIO
parameter (Group 4, APR 19): 1, 1/2, 1/4, 1/8 and 1/16. These two filters
enable the ADC to operate at an oversampling ratio of N > 2. The filters
operate at the ADC sampling rate and generate down-sampled I and Q
streams from the sampled I and Q inputs. The decimation and the
sampling rate are configured to provide the highest possible number of
samples per symbol with the tightest decimation filter available. The
procedure is outlined in
Demodulator Module Functional Description
0
0
1
2
3
4
1
1
1
2
4
8
Table 5.1
10000100 0x84
10000100 0x84
00000100 0x04
00101000 0x28
01010001 0x51
01111010 0x7A
Binary
Register 19
Group 4,
Setting
and the results are shown in
Hex
91.5 (N = 1, S = 61, T = 10,
See footnote
See footnote
See footnote
See footnote
See footnote
Fs (MHz)
M = 3
Table
2
5.2.