L64724 LSI Logic Corporation, L64724 Datasheet - Page 218

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

B.1.2 Clock Loop
B.1.3 Carrier Loop
B.1.4 QPSK Demodulator Debugging Summary
B-4
Set the loop bandwidth according to
CLK_LCF status bit (Group 3, APR 11, bit 3) indicates whether the clock
loop is locked.
The following steps show how to set up the carrier loop.
1. Set the CAR_SW bit to 1 the and CAR_OPEN bit to 0 in the Carrier
2. Change the upper and lower sweep limits registers (CAR_USWL and
3. Change the value in the Carrier Sweep Rate register (CAR_SWR in
The following steps summarize how to debug the QPSK Demodulator
portion of a system that includes the L64724.
1. Ensure that the AGC loop functions properly.
2. Ensure that the clock loop is locked.
3. Set the CAR_SW and CAR_OPEN bits in the Carrier Loop
4. If the carrier still does not lock, check the CAR_SWP parameter and
5. If the carrier seems to lock and stops sweeping, check the Carrier
L64724 Application Notes
Loop Configuration register (Group 4, APR 41). These bit settings
force the sweep to begin. Auto sweep can be selected to sweep
between upper and lower sweep limits.
CAR_LSWL in Group 4, APR 34–37) and observe CAR_NCOF
(Group 3, APR 7).
Group 4, APR 32 and 33). If the sweep rate is fast, you may not be
able to turn the sweep off fast enough through manual intervention,
the microcontroller will have to do this in real time.
Configuration register to 0b01. The loop should now lock or at least
slow down near the center of the frequency range.
recalculate the loop constant values if needed. Each one of these
parameters affects the behavior of the loop.
and FEC Synchronization Status register (Group 3, APR 11) for the
status. All flags should be set to 1 when the carrier and clock are
locked.
Equation
5.8, on
page
5-10. The