L64724 LSI Logic Corporation, L64724 Datasheet - Page 27

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

2.7 Analog-to-Digital Converter (ADC) Interface
COEn
DVALIDOUT
ERROROUTn Error Detection Flag
FSTARTOUT Frame Start Output
The ADC module converts the incoming IVIN and QVIN signals into an
internal 6-bit digital representation for processing. The following pins
support the ADC module.
Analog-to-Digital Converter (ADC) Interface
Channel Output Enable
When asserted, the COEn signal enables the
ERROROUTn, CO[7:0], DVALIDOUT, BCLKOUT, and
FSTARTOUT pins. Operation of the receiver continues
regardless of the state of the COEn signal.
Valid Data Out
The DVALIDOUT signal indicates that the CO[7:0] signals
contain the corrected channel data. New data is valid on
the CO[7:0] signals when the DVALIDOUT signal is
asserted. DVALIDOUT is not asserted during the propa-
gated check and GAP bytes. The DVALIDOUT signal is
deasserted after the FEC_RST register bit (Group 4,
APR 55) is set to a 1.
The L64724 asserts the ERROROUTn pin (LOW) to flag
uncorrectable errors. The L64724 asserts the
ERROROUTn signal at the beginning of any frame that
contains an uncorrectable error, and deasserts it at the
end of the frame if the error condition is removed. The
ERROROUTn signal is exactly aligned with the output
data stream and is asserted after the FEC_RST register
bit (Group 4, APR 55) is set to a 1. The Errorout_Invert
bit (Group 4, APR 31), when set to 1, changes the active
state of the ERROROUTn signal from active-LOW to
active-HIGH.
The L64724 asserts the FSTARTOUT signal during the
first bit of every frame with valid data in Serial Channel
Output mode and during the first byte in Parallel Channel
Output mode. FSTARTOUT is valid only when the
DVALIDOUT signal is asserted. The FSTARTOUT signal
is deasserted after the FEC_RST register bit (Group 4,
APR 55) is set to a 1.
Output
Output
Output
Input
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