L64724 LSI Logic Corporation, L64724 Datasheet - Page 59

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

3.5.8 RI Read Back (Group 3: APR 12)
3.5.9 RQ Read Back (Group 3: APR 13)
S1
The RI Readback register displays the digital value on the I channel
input.
Read/Write: R
Reserved
RI
The RQ Readback register displays the digital value on the Q channel
input.
Group 3: Status Registers
APR
12
D7
Reserved
Deinterleaver/Reed-Solomon Decoder is not
synchronized.
Stage 1 Synchronization Flag
The L64724 sets the S1 bit to 1 when the Viterbi Decoder
synchronization module is in synchronization. When the
bit is 0, the Viterbi Decoder is not synchronized.
Reserved
These bits are reserved for LSI Logic internal use only.
When read, they return an indeterminate value.
RI Read Back
This register displays the value on the RI[5:0] input bus.
Note that PCLK needs to be running for this feature to
operate properly.
D6
S2
S1
0
1
0
1
D5
Definition
Deinterleaver/Reed-Solomon Decoder Out
of Synchronization
Deinterleaver/Reed-Solomon Decoder In
Synchronization
Definition
Viterbi Decoder Out of Synchronization
Viterbi Decoder In Synchronization
RI[5:0]
Reset Value: 0x00
D0
[7:6]
[5:0]
3-29
0