L64724 LSI Logic Corporation, L64724 Datasheet - Page 148

• Manufacturer Part Number: L64724
• Description: Satellite Receiver
• Manufacturer: LSI Logic Corporation

5.7.1.6 False Locks
5.7.2 Carrier Phase Tracking
5.7.2.1 Phase Error Estimator
5-16
The phase lock detector uses a internal threshold and an estimation
period, which are programmable using the CAR_LC_THSL register
(Group 4, APR 29).
The FP_LOCK_LEN bit (Group 4, APR 54) selects between a long and
short estimation period. For operation at low E
long period should be selected (FP_LOCK_LEN = 0). A typical value of
CAR_LC_THSL is then 31.
For operation at higher E
selected, which provides for a faster lock detection. In this case, a typical
value for CAR_LC_THSL is 72.
The microcontroller must take particular care to handle a false lock
condition correctly. A false lock occurs when phase lock has been
detected but the correct central frequency has not yet been reached.
This situation occurs in QPSK for frequency offsets that are multiples of
1/4 T, where T is the QPSK symbol duration, and also at other offsets
dictated by the discrete nature of the carrier recovery loop. Offsets that
are not multiples of 1/4 T are hard to predict.
The following subsections give a detailed description of the phase error
estimator and the carrier recovery loop characteristics.
In QPSK mode (the QB bit in Group 4, APR 2 is 0), the phase error
detector implements two error estimators:
The microcontroller selects the estimator using the CAR_PED_SEL bit
(Group 4, APR 41). When the CAR_PED_SEL is 0, the DDML estimator
is used. When the bit is 1, the NDAML estimator is used.
In BPSK mode (the QB bit is 1 in Group 4, APR 2), the phase error
detector implements a single DDML estimator.
Demodulator Module Functional Description
Nondata Aided Maximum Likelihood (NDAML)
Decision Directed Maximum Likelihood (DDML)
b
/N
o
(10 dB or higher), the short period can be
b
/N
o
(less than 10 dB), the