S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 77

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S1K50000

Manufacturer Part Number
S1K50000
Description
Design Guide S1k50000 Series
Manufacturer
Epson Electronics America, Inc.
Datasheet
Chapter 5: Propagation Delay Time and Timing Design
72
The flip-flop setup/hold times of the S1K50000 series are listed in cell libraries in the form
shown in Table 5-4 below. During actual use, please see the timing characteristics of each
individual cell.
Note: P = transition from 0 to 1 level or Positive pulse
R E S E T
S E T
S E T
N = transition from 1 to 0 level or Negative pulse
R(P) to S(P)
C(P) to D
C(P) to R
C(P) to S
Figure 5-5 Timing Waveform Diagram 2 (explanation diagram for (6) through (7))
C(N)
R(N)
C(P)
S(N)
Pin
RELEASE
(SETUP)
Table 5-4 Timing Characteristics of KDFSR (Reference)
Typ. (V
Setup time (ps)
DD
610
367
415
643
RELEASE
(HOLD)
= 3.3 V)
EPSON
Typ. (V
Hold time (ps)
DD
291
468
437
= 3.3 V)
STANDARD CELL S1K50000 SERIES
Typ. (V
Pulsewidth (ps)
1022
1031
DD
991
891
DESIGN GUIDE
= 3.3 V)

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