S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 21

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

Chapter 2: Precautions on Circuit Design
16
[Dedicated buffers]
Choose the dedicated buffer from among those listed below, in accordance with the fan-out.
Note 1: The K value of these cells (delay due to fan-out) is set to 0 in pre-simulation.
Note 2: The fan-out counts for these cells are set to infinity.
Note 3: The delay relative to the fan-out counts is only an approximate value for use as a guideline.
[Restrictions and precautions]
• Applicable series: S1L9000F, S1L30000, S1L35000, S1L50000, S1K50000
• The dedicated buffers can only be used for the purpose of Clock Tree Synthesis.
• Clock Tree Synthesis can also be applied to data lines or other control signals. However, if
• The application of Clock Tree Synthesis to nets with a small fan-out may result in increased
• Clock Tree Synthesis may also help to adjust the skew between multiple clock lines. In such
• For a set of clock lines that have the same clock root and are divided into multiple clock lines
the number of nets to which Clock Tree Synthesis is applied increases, a large skew or delay
may result. Therefore, limit the number of synthesized nets to 10, and limit the application of
synthesis to critical nets with a large fan-out.
delay or skew. Apply synthesis only to nets that have a fan-out of several tens or more.
a case, consult Seiko Epson after presenting a detailed block diagram (clearly showing the
clock-line structure).
by gates or the like, “Gated Clock-Tree Synthesis Explanation Data” is separately required.
In such a case, contact Seiko Epson.
Cell Name
KCRBF2
KCRBF3
KCRBF4
KCRBF5
KCRBF6
KCRBF7
KCRBF8
S1K50000 Series
To Max. (ns)
EPSON
2.00
3.00
4.00
5.00
6.00
7.00
8.00
Approximate Fan-Out Count
STANDARD CELL S1K50000 SERIES
3000 to 10000
500 to 3000
Over 10000
0 to 500
DESIGN GUIDE