S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 64

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

STANDARD CELL S1K50000 SERIES
DESIGN GUIDE
6) Creating test patterns
b. Dedicated AC path measurement mode
In order for AC and DC tests to be conducted efficiently, customers are requested to design
a test circuit as well as a test pattern.
Figure 4-2 shows an example test pattern for the example test circuit shown in Figure 4-1.
Note the following in the design of a test pattern:
a. Create a test pattern like the one shown in the example separately from the patterns
b. All pins used in the circuit must be written in this test pattern.
c. Also write test pins (e.g., TSTEN) in the patterns used to verify the circuit’s functionality.
d. When the input level of the test pin (e.g., TSTEN) is high (= 1), all of the pull-up/pull-
used to verify the circuit’s functionality. Seiko Epson creates only the test patterns of the
input logic level inspection mode.
In such a case, make sure the input level of the test pin (e.g., TSTEN) is low (= 0).
down resistors are disabled (inactive).
TST
TSTEN
INP0
INP1
INP2
0
1
1
1
1
1
1
1
1
1
1
ILG
X
X
X
X
X
X
X
X
X
1
0
INPUT
TM2
X
X
X
1
1
1
0
0
0
1
0
TM1
Table 4-2 Test-Circuit Truth Table
X
X
X
1
1
0
1
0
1
0
0
. . .
. . .
. . .
. . .
TM0
X
X
X
1
0
1
1
1
0
0
0
EPSON
Chapter 4: Circuit Design Taking Testability into Account
TS
0
1
1
1
1
1
1
1
1
1
1
TD
X
X
0
1
1
1
1
1
1
0
0
High
Low
Low
High/low input
TE
OUTPUT
X
X
0
1
1
1
1
0
0
0
0
TAC
X
X
0
1
1
1
1
1
1
1
0
OLG
X
X
X
X
X
X
X
X
0
1
0
MS
X
X
0
0
0
0
0
1
0
0
0
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