S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 6

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

Chapter 1 Overview
1.1 Features
STANDARD CELL S1K50000 SERIES
DESIGN GUIDE
Seiko Epson’s S1K50000 series consists of high-function, high-integrated CMOS standard
cells based on the 0.35-micron process.
• High degree of integration
• Operating speed
• Process
• I/F level
• Input mode
• Output mode
• Drive output
• Supports dual-power-supply operation using an internal level shifter
• Capable of operating with V
Maximum of 1,456,000 gates (2-input NAND gate equivalents)
Internal gate:
Input buffer:
Output buffer: 2.12 ns (5.0 V typ.) using a level shifter,
CMOS 0.35-µm Al 3/4-layer metalization
Input/output TTL-, CMOS-, and LVTTL-compatible
TTL, CMOS, LVTTL, TTL Schmitt, CMOS Schmitt, LVTTL Schmitt, and
PCI
Internal pull-up and pull-down resistors available (two resistance val-
ues each)
Normal, tri-state, bidirectional, or PCI
I
I
I
(Internal logic: low-voltage operation; input/output buffers: high- and
low-voltage interfaces usable in combination)
OL
OL
OL
= 0.1 mA, 1 mA, 3 mA, 8 mA, 12 mA, or 24 mA selectable (when a
= 0.1 mA, 1 mA, 2 mA, 6 mA, or 12 mA selectable (at 3.3 V)
= 0.05 mA, 0.3 mA, 0.6 mA, 2 mA, or 4 mA selectable (at 2.0 V)
DD
5.0-V level shifter is used)
= 2.0 V ± 0.2 V
136 ps (3.3 V typ.), 224 ps (2.0 V typ.)
(2-input POWER NAND, standard wiring load)
380 ps (5.0 V typ.) using a level shifter,
400 ps (3.3 V typ.), 1.30 ns (2.0 V typ.)
(standard wiring load)
2.02 ns (3.3 V typ.), 3.90 ns (2.0 V typ.) (CL = 15 pF)
EPSON
Chapter 1: Overview
1