S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 72

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

5.3 Load Due to Input Capacitance (Load A)
STANDARD CELL S1K50000 SERIES
DESIGN GUIDE
The delay time in a logic gate depends on the sum total of the input capacitances of the logic
gates (fan-in) connected to the output pin of that gate. The input capacitance of each gate
(fan-in) and the loading limits of their output pin (fan-out) are listed in the “Standard Cell
S1K50000-Series MSI Cell Library.”
In the design of a circuit, make sure the sum total of fan-in will not exceed the output pin’s fan-
out.
The fan-in values for KIN2, KNA2, and KNO2 are given in Table 5-2. Their sum is the value of
• Example of the calculation of Load A
Load A.
The following shows an example of the calculation of Load A using the circuit diagram
shown in Figure 5-1 and the data given in Table 5-2.
Load A (N1) = (Fa n-i n o f KIN2) + ( Fan - i n o f KNA2)
KNO2
KNA2
KIN1
KIN2
cell
Table 5-2 Data Used for Example Load-A Calculation
Figure 5-1 Circuit for Example Load-A Calculation
= 2.0 + 1 + 1 = 4.0
Pin
A1
A2
A1
A2
A
A
KIN 1
Input
EPSON
Fan-in
1.0
2.0
1.0
1.0
1.0
1.0
2.0
1
1
Chapter 5: Propagation Delay Time and Timing Design
KIN 2
KNA 2
KNO 2
+ ( Fa n -i n o f KNO2)
Pin
X
X
X
X
Output
Fan-out
17.7
36.9
15.4
8.9
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