S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 29

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

Chapter 2: Precautions on Circuit Design
24
(7) Logic circuit design rules for ATPG support (DFT)
• Scan clock input pin
In order for ATPG to be performed, the logic circuit is scanned. In the creation of the
original circuit, be sure to follow the rules specified below to ensure that it will have good
observability. Practical examples are shown below. If these measures are difficult to
implement or there are any uncertainties about them, contact Seiko Epson.
• Applicable series: S1L50000, S1L30000, S1L9000F, S1X50000, S1K50000
• Prepare one scan enable input pin (SCANEN) as a dedicated input pin.
• Submit “trial data” to Seiko Epson one week prior to the release of the formal data. This
• The clock, reset, and set inputs of all flip-flops to be scanned must be controllable directly
• Circuit design using scan flip-flops in the original circuit is inhibited.
• Skew consideration for clock nets by Clock Tree Synthesis must be supported.
• I/O cells must be placed on the top hierarchical level.
This clock input pin is in the test pattern generated by ATPG. In most cases, this pin uses
the system clock during normal operation.
trial data is necessary to preliminarily check your circuit prior to formal data-in, in order to
increase the efficiency of work following formal data-in and achieve a high fault detection
rate.
from the external pins.
If not controllable, configure a controllable circuit by attaching an ATPG test input pin
(ATPGEN) separately from the SCANEN pin.
If the flip-flops are configured to have multiple clocks fed from external pins, make
sure all of the flip-flops to be scanned basically operate with a single clock input
when ATPGEN is active. However, if two or more of such circuit configurations exist,
consult Seiko Epson.
ATPGEN
CLK
Figure 2-10 Example of Processing of the Clock Line
XIBC
XIBCD1
LOGIC
EPSON
KAO24A
KCRBF*
STANDARD CELL S1K50000 SERIES
D
C XQ
D
C XQ
KDF
KDF
Q
Q
DESIGN GUIDE