S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 73

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

Chapter 5: Propagation Delay Time and Timing Design
5.4 Load Due to Wiring Capacitance (Load B)
5.5 Calculating the Propagation Delay Time
68
The load due to the wiring capacitance between cells (Load B) is characteristic, in that exact
values for it cannot be calculated until placement & routing are actually performed. However,
there is a certain correlationship between Load B and the number of wiring branches (number
of nodes) connected to the outputs of cells, making it possible to statistically predict an
assumed value. The assumed wiring capacitance of each master is listed in the “Standard
Cell S1K50000-Series MSI Cell Library.”
The following shows an example of the calculation of the propagation delay time using the
circuit shown in Figure 5-2 (operating at 3.3 V) and the data given in Table 5-3.
KNA2
KIN1
KIN2
Cell
Figure 5-2 Circuit for Example Calculation of the Propagation Delay Time
Pin
A1
A
A
Input
Table 5-3 Characteristics of Cells (Power-Supply Voltage of 3.3 V)
Fan-in
1.0
2.0
1.0
A
Pin
KIN 1
X
X
X
Output
Fan-out
17.7
36.9
15.4
P
EPSON
2.0
1
1
KIN 2
KNA 2
KNO 2
From
A1
A
A
To
X
X
X
STANDARD CELL S1K50000 SERIES
t
pd
B
C
D
Edge
(Typ.)
T
0
42
41
32
32
57
59
(ps)
DESIGN GUIDE
K (ps/LU)
20.9
15.0
10.1
20.1
25.2
7.1