S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 67

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

Chapter 4: Circuit Design Taking Testability into Account
4.4 Test Circuit for Functional Cells
4.4.1 Configuration of a Test Circuit
4.4.2 Test Patterns
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When functional cells are used, huge numbers of test patterns and large amounts of time are
required to verify the operation of the entire circuit (including the user circuit). Therefore,
customers are requested to design a test circuit in such a way that operation of the functional
cells and user circuit can be verified as single units.
In the design of a test circuit, note the following.
(1) Add a test circuit so that each functional cell and the user circuit can be separated and
(2) Even when fixing the inputs of the functional cells to V
(3) Even when not using the output pins of the functional cells, install a test circuit to allow all
(4) Do not use multiple output or input pins of the functional cells collectively as one test-
(5) Do not use a sequential circuit in a test circuit that is used to test the functional cells.
(6) Do not feed an input signal from the test input pin into the function cells after inverting its
(7) If the functional cell’s input and output pins are led out directly as pins of the IC, it is not
(8) Do not use bidirectional buffers with a pull-up for the test-mode switch pin. Bidirectional
The test patterns that must be created by customers are items 1) and 2) above. The test
pattern in item 3) does not need to be created by customers. Existing test patterns at Seiko
Epson are used.
Please note, however, that the test patterns for the functional cells (i.e., the existing test
patterns) cannot be disclosed to customers.
Broadly classified, there are the following three types of test patterns:
measured individually for each block, with the pins of the functional cells leading out to
external pins.
enable test input.
outputs of the functional cells to be observed from external pins.
shareable pin.
logic level. In addition, do not forward the output signals of the functional cells to the test
output pin after inverting their logic level.
necessary to attach a test circuit.
buffers with a pull-down are acceptable.
1) Test pattern for testing only the user circuit
2) Test pattern for testing the entire circuit
3) Test pattern for testing only the functional cells
EPSON
SS
or V
DD
STANDARD CELL S1K50000 SERIES
, install a test circuit to
DESIGN GUIDE