S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 17

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

Chapter 2: Precautions on Circuit Design
2.6 Internal Bus Circuits
12
A bus circuit is configured with 3-state logic circuits, so one of the outputs connected to the
bus can be driven active (while the other outputs are placed in the high-impedance state) by
turning the bus control signals on or off.
In this way, a transmission-signal line on the bus is shared by dividing it in time. Although bus
circuits are very effective for logic design, note the following when using a bus circuit.
Precautions on the use of bus circuits
(1) Bus cells can only be used for bus circuits (for the S1K50000-series bus cells, see Table 2-1).
(2) When using bus cells, add bus definition cells KBLT to the bus in the configuration of your
(3) Up to 32 bus cells can be connected to one length of bus.
(4) Of the bus cells connected to one length of bus, only one output can be active (0 or 1) at
(5) Even when all of the bus cells connected to one length of bus are in the high-impedance
(6) In the creation of your test pattern, make sure the bus’ initial state will settle easily, to
(7) The bus control signals within the same event rate can be switched only once.
(8) Excessive fan-out of the bus circuit may cause the propagation delay time to increase,
circuit.
one time, and all other bus cell outputs must be placed in the high-impedance state (Z).
state (Z), data may be retained by a bus latch cell. However, the retained data should be
left floating, and should not be used as logic signals.
ensure improved testability. In addition, add one or more test pins to make the bus easily
controllable.
making high-speed operation difficult.
EPSON
STANDARD CELL S1K50000 SERIES
DESIGN GUIDE