S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 31

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

Chapter 2: Precautions on Circuit Design
26
(8) Other
• Fix the outputs of non-scanned flip-flops.
• Depending on the number of scanned flip-flops, the number of gates increases by
• The period required for DFT and ATPG depends on the circuit configuration and gate
• Prior to data-in, please send the “ATPG check sheet” and “external pin information” to Seiko
approximately 15% to 20% compared to that in the original circuit.
size. The DFT and ATPG work at Seiko Epson requires at least three days, which should
be taken into account in your plan. (In some cases, depending on the circuit configura-
tion, approximately 10 days may be required. Therefore, please carefully examine the
presented materials when designing your circuit.)
Epson. If circuit changes are required, you will be requested to make them. The test pattern
interfaced to Seiko Epson should include definitions of the external pins (e.g., ATPGEN and
SCANEN) for scan purposes.
For ATPG support, CTS (Clock Tree Synthesis) is essential during placement and routing.
Therefore, please submit the necessary information for Clock Tree Synthesis specified on
page 15, along with said information.
The outputs of MSI macros that include T-flip-flops or flip-flops, as well as those of
non-scanned flip-flops, cause malfunction in the ATPG test pattern or hinder fault
detection. Therefore, fix their outputs using the ATPGEN pin as much a as possible.
SCANEN
ATPGEN
Figure 2-12 Example of the Processing of Bidirectional Pins
XIBCD1
XIBCD1
EPSON
XBC1
XBC1
XBC1
A
E
A
E
A
E
STANDARD CELL S1K50000 SERIES
SCANOUT
SCANIN
D0
D1
D2
DESIGN GUIDE