S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 34

Manufacturer Part Number

S1K50000

Description

Design Guide S1k50000 Series

Manufacturer

Epson Electronics America, Inc.

Datasheet

1.S1K50000.pdf (131 pages)

STANDARD CELL S1K50000 SERIES

DESIGN GUIDE

<Other>

• Number of gates (BC) prior to scan cell insertion : __________

• Total number of D and JK ﬂip-ﬂops

• Expected date of trial data presentation: ( ______Month, _______day, _______year)

• Desired fault detection rate

• Along with this sheet, materials that will help to conﬁrm circuit blocks, hierarchical levels

Note 3: If not inserted in the original circuit, please specify your desired contents.

Note 4: Unless a speciﬁc request to the contrary is made, pins will be assigned by Seiko

(Trial data: Check sheet, preliminary netlist, tentative pin arrangement table, circuit block

diagram)

(module and instance names), and data paths between clock lines and blocks are

requested.

• Input pins that cannot be assigned for scan data input (Note 4)

• Output pins that cannot be assigned for scan data output (Note 4)

• Remarks

______________________________________________________________

Epson.

EPSON

: __________

: ____ %

Chapter 2: Precautions on Circuit Design