S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 54

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

3.4 Gated I/O Cells
3.4.1 Outline of Gated I/O Cells
3.4.2 Features of Gated I/O Cells
3.4.3 Precautions on the Use of Gated I/O Cells
STANDARD CELL S1K50000 SERIES
DESIGN GUIDE
Seiko Epson’s S1K50000 series of Gated I/O cells make it possible to provide input to pins in
the floating or Hi-Z state without the use of pull-up or pull-down circuits, an operation that was
conventionally impossible. They also make it possible to cut off the high-voltage-side (HV
power supply in a multi-power-supply design. Two types are available: one in which the power
supply is cut off when the control-signal level is high, and another in which the power supply is
cut off when the control-signal level is low, allowing the level for cutting off the power supply to
be chosen in accordance with the circuit design.
(1) Without limitations on the number of cells used or their placement, the Gated I/O cells can
(2) In a multi-power-supply design, the high-voltage-side (HV
(3) Inputs can be placed in the Hi-Z state without the use of pull-up or pull-down circuits.
(4) The supported input levels are the TTL level (when HV
(5) Two types are available: one in which the power supply is cut off when the control-signal
(6) Because the Gated I/O cells are entirely of a CMOS structure, they help to reduce the
(1) The Gated I/O cells cannot be subjected to Seiko Epson’s standard input-level
(2) When inputs are placed in the Hi-Z state using Gated I/O cells, the power supply must be
be positioned as desired by customers, providing freedom in circuit design.
However, because special measures are needed, if such a cut-off function is desired,
contact Seiko Epson or its distributor.
the LVTTL level (when HV
level is high, and another in which the power supply is cut off when the control-signal level
is low.
chip’s power consumption.
determination due to the circuit configuration. Therefore, if it is necessary for the input level
to be determined by a tester, a test circuit must be configured separately. For an example
of a test circuit, see Figure 3-6.
cut off through control of the Gated I/O cell before the pin inputs float to a Hi-Z state. If
inputs are placed in the Hi-Z state without the performance of this cut-off, a large current
flows into the LSI as with ordinary cells, causing the device to malfunction. The same
applies to the performance of connecting operations using control of the Gated I/O cell
while inputs are left floating. In such a case, the logic levels latched into the device’s
internal logic cannot be guaranteed. Before you cut off the power to the high-voltage side
(HV
this case.
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), first contact EPSON’s marketing division, as a special procedure is also required in
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and LV
Chapter 3: Types of Input/Output Buffers and Usage Precautions
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EPSON
= both 3.3 V; or V
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and LV
= 3.3 V).
) power supply can be cut off.
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= 5.0 V and 3.3 V) or
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49
)