S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 76

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

STANDARD CELL S1K50000 SERIES
DESIGN GUIDE
(4) Release time (setup)
(5) Release time (hold)
(6) Set/reset setup time
(7) Set/reset hold time
For details on the timing error messages output during simulation, see the user’s manual of
each tool.
( R E S E T )
( R E S E T )
In flip-flops and MSIs consisting of flip-flops, the time before the clock pulse can change
state after a set/reset input has been deasserted is referred to as the “release time.”
In flip-flops and MSIs consisting of flip-flops, the set/reset input state must be maintained
after an active clock pulse is entered. This time is referred to as the “release time (hold).”
In flip-flops and MSIs consisting of flip-flops, the time before a reset input can be asserted
after a set input has been deasserted is referred to as the “set/reset setup time.”
In flip-flops and MSIs consisting of flip-flops, a reset signal once asserted must be held
active until the next time a set signal is asserted. This time is referred to as the “set/reset
hold time.”
C L O C K
DATA
S E T
S E T
Figure 5-4 Timing Waveform Diagram 1 (explanation diagram for (1) through (5))
RELEASE
(SETUP)
SETUP
SET
DATA
CLOCK
RESET
RELEASE
(HOLD)
Figure 5-3 KDFSR
HOLD
EPSON
D
C
Chapter 5: Propagation Delay Time and Timing Design
S
R
XQ
Q
XQ
Pulse
Width
Q
Pulse
Width
Pulse
Width
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