S1K50000 Epson Electronics America, Inc., S1K50000 Datasheet - Page 60

• Manufacturer Part Number: S1K50000
• Description: Design Guide S1k50000 Series
• Manufacturer: Epson Electronics America, Inc.

Chapter 4 Circuit Design Taking Testability into
4.1 Consideration for Circuit Initialization
4.2 Consideration for Reduction of the Test-Pattern Size
STANDARD CELL S1K50000 SERIES
DESIGN GUIDE
Prior to the shipment of standard cells from the factory, a product test is conducted through the
use of an LSI tester.
Therefore, testability must fully be taken into account in the circuit design. Consider the
following points in the design of a circuit.
Many flip-flops are used in a circuit. However, when tests are conducted using an LSI tester or
a circuit is simulated, all of the flip-flops in the initial state are in an X (indeterminate) state.
Therefore, depending on the circuit configuration, it will be impossible to initialize the circuit, or
a huge test pattern may be required for initialization.
Therefore, in the design of a circuit, use flip-flops with a reset input or take other similar
measures to ensure that the circuit can be initialized easily.
As the circuit size increases, so does the size of the test pattern. However, test patterns are
subject to the following limitations imposed by an LSI tester.
These limitations apply to all types of test patterns, such as those for DC testing, for Z
inspection, for a test circuit, and ROM or megacell test patterns prepared by Seiko Epson. For
details on the number of ROM and megacell test patters and the number of events in those
test patterns, contact Seiko Epson or its distributor. Regarding test patterns for RAM testing,
please note that although the reference patterns prepared by customers are included in those
that are subject to said limitations, the full test patterns for RAM to be prepared by Seiko
Epson are not included.
In the design of a circuit, incorporate measures to increase its testability, thereby reducing the
size of the test patterns required for it by, for example, installing a test pin that allows a clock to
be fed into the middle of multistage counters or adding a test pin that allows the LSI’s internal
signals to be monitored.
Number of events per test pattern
Number of test patterns
Total number of events in test patterns
Account
EPSON
Chapter 4: Circuit Design Taking Testability into Account
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