TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 85

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

(2) Event counter mode
contents of TC2DR are compared with the contents of the up counter. If a match is
found, an INTTC2 interrupt is generated, and the counter is cleared. The minimum
input pulse width of TC2 pin is shown in Table 2.8.2. Two or more machine cycles are
required for both the “H” and “L” levels of the pulse width. Match detect is executed on
the falling edge of the TC2 pin. A match can not be detected and INTTC2 is not
generated when the pulse is still in a falling state.
“H” width
“L” width
In this mode, events are counted on the rising edge of the TC2 pin input. The
Example: Sets the event counter mode and generates an INTTC2 interrupt 640 counts later.
Table 2.8.2 Timer/Counter 2 External Clock Source
NORMAL1/2, IDLE1/2 Mode
LDW
DI
SET
EI
LD
LD
2
2
3
3
/fc
/fc
Minimum Input Pulse Width [s]
(TC2DR), 640
(EIRE). 4
(TC2CR), 00011100B
(TC2CR), 00111100B
86FM48-81
SLOW1/2, SLEEP1/2 Mode
;
;
;
;
;
;
2
2
Sets TC2DR
IMF = “0”
Enables INTTC2 interrupt
IMF = “1”
TC2CK ← “111”, TC2M ← “0”
Starts TC2
3
3
/fs
/fs
TMP86FM48
2007-08-24