TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 48

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

Internal reset
1.6.2
1.6.3
1.6.4
Instruction
execution
Note 1: Address “a” is in the SFR or on-chip RAM (WDTCR1<ATAS> = “1”) space.
Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.
Address-Trap-Reset
fetch an instruction from the on-chip RAM (when WDTCR1<ATAS> is set to “1”) or the SFR
area, address-trap-reset and the Flash reset will be generated. The reset time is maximum
24/fc [s] + 2
Note: The operating mode under address trapped is alternative of reset or interrupt. Address
Watchdog Timer Reset
System-Clock-Reset
prevent dead lock of the CPU. (The oscillation is continued without stopping.)
the maximum reset period is 24/fc [s] + 2
If the CPU should start looping for some cause such as noise and an attempt be made to
Refer to Section “2.4 Watchdog Timer”.
If the condition as follows is detected, the system clock reset occurs automatically to
- In case of clearing SYSCR2<XEN> and SYSCR2<XTEN> simultaneously to “0”.
- In case of clearing SYSCR2<XEN> to “0”, when the SYSCR2<SYSCK> is “0”.
- In case of clearing SYSCR2<XTEN> to “0”, when the SYSCR2<SYSCK> is “1”.
When the system clock reset is generated, the flash reset is also generated. Therefore,
trap or no address trap can be selected by WDTCR1<ATAS> for the internal RAM.
JP
10
/fc [s] (65.5 µs at 16.0 MHz).
a
max 24/fc [s]
Address trap is occurred
Figure 1.6.2 Address-Trap-Reset
for Flash reset
2
10
/fc [s]
86FM48-44
10
/fc [s] (65.5 µs at 16.0 MHz).
4/fc to 12/fc [s]
Reset release
16/fc [s]
Instruction at address r
TMP86FM48
2007-08-24