TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 119

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

INTSBI interrupt
INTSBI
PIN
SDA pin
SCL pin
request
PIN
Figure 2.12.14 Termination of Data Transfer in Master Receiver Mode
b.
Table 2.12.3 The Behavior of INTSBI and PIN after Losing Arbitration
When the Arbitration Lost Occurs during
Transmission of Slave Address as a Master
When the slave address matches the value set by
I2CAR, the PIN is cleared to “0” by generating of
INTSBI. When the slave address doesn't match the
value set by I2CAR, the PIN keeps “1”.
mode or in slave mode after losing arbitration.
•
•
•
master mode. And an INTSBI interrupt request occurs when word data transfer
terminates after losing arbitration. The behavior of INTSBI and PIN after losing
arbitration are shown in Table 2.12.3.
When the MST is “0” (Slave mode)
In the slave mode, a serial bus interface circuit operates either in normal slave
In the slave mode, the conditions of generating INTSBI are follows:
A serial bus interface circuit changes to a slave mode if arbitration is lost in the
D7
“0” → ACK
Read SBIDBR
reading data which is 1-word before the last data to be received. A serial bus
interface circuit does not generate a clock pulse for the acknowledge signal by
clearing ACK. In the interrupt routine of end of transmission, when the BC is
set to “001” and read the data, PIN is set to “1” and generates a clock pulse for
a 1-bit data transfer. In this case, since the master device is a receiver, the
SDA line on a bus keeps the high-level. The transmitter receives the
high-level signal as an ACK signal. The receiver indicates to the transmitter
that data transfer is complete.
generates the stop condition to terminate transmit, generate the stop
condition to terminate data transfer.
1
When the received slave address matches to the value set by the I2CAR
When a “GENERAL CALL” is received
At the end of transferring or receiving after matching of slave address or
receiving of “GENERAL CALL”
To make the transmitter terminate transmit, clear the ACK to “0” before
After 1-bit data is received and an interrupt request has occurred,
D6
2
D5
3
INTSBI is generated at the termination of word data.
86FM48-115
D4
4
D3
5
D2
6
When the Arbitration Lost Occurs during
Transmission of Data as a Master Transmit Mode
PIN keeps “1”.
D1
7
D0
8
“001” → BC
Read SBIDBR
Acknowledge signal
sent to a transmitter
1
TMP86FM48
2007-08-24