TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 77

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

TC1 pin input
Internal clock
Up counter
TC1DRA
INTTC1 interrupt
TC1 pin input
Internal clock
Up counter
TC1DRA
INTTC1 interrupt
(4) Window mode
?
Command start
?
Command start
“H” width
logical AND-ed product of the TC1 pin input (Window pulse) and an internal clock. The
contents of TC1DRA are compared with the contents of up counter. If a match is found,
an INTTC1 interrupt is generated, and the counter is cleared. It is possible to select
either positive logic or negative logic for the TC1 pin input (by using the TC1 start
control TC1CR<TC1S>).
count can be analyzed by program. To put another way, the frequency of the applied
pulse must be sufficiently low, compared with that of the internally set source clock.
“L” width
In this mode, counting up is performed on the rising edge of the pulse that is the
The maximum frequency that can be applied to the pin must be such that the related
7
9
Count start
0
Table 2.7.2 Timer/Counter 1 External Clock Source
NORMAL1/2, IDLE1/2 Mode
Count start
Figure 2.7.6 Window Mode Timing Chart
1
0
2
1
2
2
(a) Positive logic (at TC1S = 10)
3
3
/fc
/fc
Minimum Input Pulse Width [s]
(b) Negative logic (at TC1S = 11)
3
2
86FM48-73
Count stop
4
3
4
Count stop
SLOW1/2, SLEEP1/2 Mode
5
5
Match detect
Count start
6
2
2
6
3
3
/fs
/fs
Count start
7 0
Counter clear
Match detect
1
7
8
2
TMP86FM48
9 0
Counter clear
3
2007-08-24
1