TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 144

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

Key-On Wake-Up Control Register
STOPCR
(1FFE
2.14.2 Control
H
)
Terminal name
STOP0EN STOP1EN STOP2EN STOP3EN
STOP0EN
STOP1EN
STOP2EN
STOP3EN
(STOPCR). It can be configured as enable/disable in 1-bit unit.
be exited by detecting low level of STOP0 to STOP3 pins, which are enabled by STOPCR,
for releasing STOP mode (Note 1). Also, because each level of the STOP0 to STOP3 can be
confirmed by reading P6DR, check all STOP0 to STOP3 pins that is enabled by STOPCR
before the STOP mode is started (Note 2, 3).
Note 1: When the STOP mode is used by edge-sensitive mode (SYSCR1<RELM> = “0”), all bit
Note 2: When the
Note 3: When confirms the level of STOP0 to STOP3 pin which is enabled by STOPCR, the
STOP0
STOP1
STOP2
STOP3
7
P64 to P67 (STOP0 to STOP3) pin can controlled by key-on wake-up control register
STOP mode can be entered by setting up the system control register1 (SYSCR1), and can
STOP
of STOPCR (STOP3EN to STOP0EN) should be cleared to “0”.
STOPCR is low, executing an instruction which starts STOP mode will not place in
STOP mode but instead will immediately start the release sequence (Warm-up).
corresponding bit of P6CR1 should be cleared to “0” before reading P6DR.
Stop mode released by P64 port
Stop mode released by P65 port
Stop mode released by P66 port
Stop mode released by P67 port
6
Table 2.14.1 Input Edge (Level) of Stop Mode Release
As both terminal
Figure 2.14.2 Key-On Wake-Up Control Register
STOP
P64/AIN04
P65/AIN05
P66/AIN06
P67/AIN07
P20/
5
INT5
pin input is high or STOP0 to STOP3 pin input which is enabled by
4
86FM48-140
SYSCR1<RELM> = “1”
3
−
“H” level (Note2)
“L” level
(Note 2)
2
−
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
Release edge (Level)
1
−
SYSCR1<RELM> = “0”
0
−
Do not use key on
wake up function
Rising edge
(Note 1)
(Initial value: 0000 ****)
TMP86FM48
2007-08-24
Write
only